Added ADC reset after each FPGA<->RPi transfer. ADC channels manipulation improved.
[fpga/rpi-motor-control.git] / pmsm-control / div8.vhdl
1
2
3 library ieee;
4 use ieee.std_logic_1164.all;
5 use ieee.numeric_std.all;
6 use work.util.all;
7
8 entity div8 is
9
10 port (
11         clk_in: in std_logic;
12         clk_out: out std_logic
13 );
14 end div8;
15
16
17 architecture behavioral of div8 is
18         signal count : std_logic_vector (2 downto 0);
19 begin
20         
21         
22         divider : process 
23         begin
24                 wait until (clk_in'event and clk_in='1');
25                 if (count="111") then
26                         count<="000";
27                 else
28                         count <= std_logic_vector(unsigned(count) + 1);
29                 end if;
30                         clk_out <= count(2);
31     end process divider;
32
33         
34                 
35 end behavioral;
36