2 -- * LXPWR slave part *
3 -- common sioreg & common counter for several ADC&PWM blocks
5 -- part of LXPWR motion control board (c) PiKRON Ltd
6 -- idea by Pavel Pisa PiKRON Ltd <pisa@cmp.felk.cvut.cz>
7 -- code by Marek Peca <mp@duch.cz>
14 use ieee.std_logic_1164.all;
15 use ieee.numeric_std.all;
18 entity rpi_mc_simple_dc is
20 gpio2: in std_logic; -- SDA
21 gpio3: in std_logic; -- SCL
22 gpio4: in std_logic; -- CLK
23 gpio14: in std_logic; -- Tx
24 gpio15: in std_logic; -- Rx
25 gpio17: out std_logic; -- RTS
26 gpio18: out std_logic; -- PWM0/PCMCLK
27 gpio27: out std_logic; -- SD1DAT3
28 gpio22: out std_logic; -- SD1CLK
29 gpio23: out std_logic; -- SD1CMD
30 gpio24: out std_logic; -- SD1DAT0
31 gpio10: in std_logic; -- SPI0MOSI
32 gpio9: out std_logic; -- SPI0MISO
33 gpio25: out std_logic; -- SD1DAT1
34 gpio11: in std_logic; -- SPI0SCLK
35 gpio8: in std_logic; -- SPI0CE0
36 gpio7: in std_logic; -- SPI0CE1
37 gpio5: in std_logic; -- GPCLK1
38 gpio6: in std_logic; -- GPCLK2
39 gpio12: in std_logic; -- PWM0
40 gpio13: in std_logic; -- PWM1
41 gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS
42 gpio16: in std_logic; -- SPI1CE2
43 gpio26: in std_logic; -- SD1DAT2
44 gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0
45 gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1
48 -- Each PWM signal has cooresponding shutdown
49 pwm: out std_logic_vector (1 to 3);
50 shdn: out std_logic_vector (1 to 3);
51 -- Fault/power stage status
52 stat: in std_logic_vector (1 to 3);
54 hal_in: in std_logic_vector (1 to 3);
60 power_stat: in std_logic;
62 adc_miso: in std_logic;
63 adc_mosi: in std_logic;
64 adc_sclk: in std_logic;
65 adc_scs: in std_logic;
67 ext_miso: in std_logic; --master in slave out
68 ext_mosi: in std_logic; --master out slave in
69 ext_sclk: in std_logic;
70 ext_scs0: in std_logic;
71 ext_scs1: in std_logic;
72 ext_scs2: in std_logic;
74 rs485_rxd: in std_logic;
75 rs485_txd: out std_logic;
76 rs485_dir: out std_logic;
81 dip_sw: in std_logic_vector (1 to 3); --na desce je prohozene cislovanni
82 -- Unused terminal to keep design tools silent
83 dummy_unused : out std_logic
88 architecture behavioral of rpi_mc_simple_dc is
89 attribute syn_noprune :boolean;
90 attribute syn_preserve :boolean;
91 attribute syn_keep :boolean;
92 attribute syn_hier :boolean;
94 -- component pll50to200
96 -- powerdown, clka: in std_logic;
97 -- lock, gla: out std_logic
102 port (A: in std_logic; Y: out std_logic);
109 a0, b0: in std_logic;
110 qcount: out std_logic_vector (31 downto 0);
111 a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
112 ab_error: out std_logic
116 signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
117 signal pwm_in, pwm_dir_in: std_logic;
118 signal gpio_clk: std_logic;
119 signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
120 signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
121 signal ce0_old: std_logic_vector(1 downto 0);
123 -- attribute syn_noprune of gpio2 : signal is true;
124 -- attribute syn_preserve of gpio2 : signal is true;
125 -- attribute syn_keep of gpio2 : signal is true;
126 -- attribute syn_hier of gpio2 : signal is true;
129 -- PLL as a reset generator
131 --zesileni signalu GPIO CLK
158 -- clka => pll_clkin,
159 -- gla => pll_clkout,
160 -- lock => pll_lock);
161 -- -- reset <= not pll_lock;
162 -- reset <= '0'; -- TODO: apply reset for good failsafe
166 dummy_unused <= gpio2 and gpio3 and gpio4 and
168 gpio12 and gpio13 and gpio14 and
169 gpio15 and gpio16 and gpio19 and
170 gpio20 and gpio21 and gpio26 and
171 stat(1) and stat(2) and stat(3) and
172 hal_in(1) and hal_in(2) and hal_in(3) and
173 irc_i and power_stat and
174 adc_miso and adc_mosi and adc_sclk and adc_scs and
176 can_rx and can_tx and
177 dip_sw(1) and dip_sw(2) and dip_sw(3) and
179 -- gpio17 and gpio18 and gpio27 and gpio22 and
180 gpio8 and gpio11 and gpio7 and gpio10 and
181 ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
198 --position is obtained on rising edge -> we should write it on next cycle
199 wait until (gpio_clk'event and gpio_clk='1');
201 --SCLK edge detection
202 spiclk_old(0)<=gpio11;
203 spiclk_old(1)<=spiclk_old(0);
207 ce0_old(1)<=ce0_old(0);
209 if (spiclk_old="01") then --rising edge, faze cteni
210 if (gpio7 = '0') then -- SPI CS must be selected
211 -- shift serial data into dat_reg on each rising edge
213 dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
215 elsif (spiclk_old="10" ) then --falling edge, faze zapisu
216 if (gpio7 = '0') then
217 gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB
222 --sestupna hrana SS, pripravime data pro prenos
223 if ((ce0_old = "10") ) then
224 dat_reg(95 downto 64) <= position(31 downto 0); --pozice
225 dat_reg(63 downto 61) <= hal_in(1 to 3); --halovy sondy
226 dat_reg(60 downto 0) <= (others => '1'); --zbytek zatim nuly