2 -- * LXPWR slave part *
3 -- common sioreg & common counter for several ADC&PWM blocks
5 -- part of LXPWR motion control board (c) PiKRON Ltd
6 -- idea by Pavel Pisa PiKRON Ltd <pisa@cmp.felk.cvut.cz>
7 -- code by Marek Peca <mp@duch.cz>
14 use ieee.std_logic_1164.all;
15 use ieee.numeric_std.all;
18 entity rpi_mc_simple_dc is
20 pwm_width : natural:=11
23 gpio2: in std_logic; -- SDA
24 gpio3: in std_logic; -- SCL
25 gpio4: in std_logic; -- CLK
26 gpio14: in std_logic; -- Tx
27 gpio15: in std_logic; -- Rx
28 gpio17: in std_logic; -- RTS
29 gpio18: in std_logic; -- PWM0/PCMCLK
30 gpio27: in std_logic; -- SD1DAT3
31 gpio22: in std_logic; -- SD1CLK
32 gpio23: in std_logic; -- SD1CMD
33 gpio24: in std_logic; -- SD1DAT0
34 gpio10: in std_logic; -- SPI0MOSI
35 gpio9: out std_logic; -- SPI0MISO
36 gpio25: in std_logic; -- SD1DAT1
37 gpio11: in std_logic; -- SPI0SCLK
38 gpio8: in std_logic; -- SPI0CE0
39 gpio7: in std_logic; -- SPI0CE1
40 gpio5: in std_logic; -- GPCLK1
41 gpio6: in std_logic; -- GPCLK2
42 gpio12: in std_logic; -- PWM0
43 gpio13: in std_logic; -- PWM1
44 gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS
45 gpio16: in std_logic; -- SPI1CE2
46 gpio26: in std_logic; -- SD1DAT2
47 gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0
48 gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1
51 -- Each PWM signal has cooresponding shutdown
52 pwm: out std_logic_vector (1 to 3);
53 shdn: out std_logic_vector (1 to 3);
54 -- Fault/power stage status
55 stat: in std_logic_vector (1 to 3);
57 hal_in: in std_logic_vector (1 to 3);
63 power_stat: in std_logic;
65 adc_miso: in std_logic;
66 adc_mosi: out std_logic;
67 adc_sclk: out std_logic;
68 adc_scs: out std_logic;
70 ext_miso: in std_logic; --master in slave out
71 ext_mosi: in std_logic; --master out slave in
72 ext_sclk: in std_logic;
73 ext_scs0: in std_logic;
74 ext_scs1: in std_logic;
75 ext_scs2: in std_logic;
77 rs485_rxd: in std_logic;
78 rs485_txd: out std_logic;
79 rs485_dir: out std_logic;
84 dip_sw: in std_logic_vector (1 to 3); --na desce je prohozene cislovanni
85 -- Unused terminal to keep design tools silent
86 dummy_unused : out std_logic
91 architecture behavioral of rpi_mc_simple_dc is
92 attribute syn_noprune :boolean;
93 attribute syn_preserve :boolean;
94 attribute syn_keep :boolean;
95 attribute syn_hier :boolean;
97 -- component pll50to200
99 -- powerdown, clka: in std_logic;
100 -- lock, gla: out std_logic
105 port (A: in std_logic; Y: out std_logic);
112 a0, b0: in std_logic;
113 qcount: out std_logic_vector (31 downto 0);
114 a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
115 ab_error: out std_logic
125 sync: in std_logic; --flag that counter "restarts-overflows"
126 data_valid:in std_logic; --indicates data is consistent
127 failsafe: in std_logic; --turn off both transistors
128 en_p, en_n: in std_logic; --enable positive & enable shutdown
129 match: in std_logic_vector (pwm_width-1 downto 0); --posion of counter when we swap output logic
130 count: in std_logic_vector (pwm_width-1 downto 0); --we use an external counter
131 out_p, out_n: out std_logic --pwm outputs: positive & shutdown
132 --TODO add the rest of pwm signals, swap match to pwm_word
138 --reset: in std_logic;
139 clk_in: in std_logic;
140 clk_out: out std_logic
144 component adc_reader is
146 clk: in std_logic; --input clk
147 adc_reset: in std_logic;
148 adc_miso: in std_logic; --spi master in slave out
149 adc_channels: out std_logic_vector (35 downto 0); --consistent data of 3 channels
150 adc_sclk: out std_logic; --spi clk
151 adc_scs: out std_logic; --spi slave select
152 adc_mosi: out std_logic --spi master out slave in
158 signal adc_reset : std_logic;
159 signal adc_channels: std_logic_vector(35 downto 0);
161 signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
162 --signal pwm_in, pwm_dir_in: std_logic;
163 signal gpio_clk: std_logic;
164 signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
165 signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
166 signal ce0_old: std_logic_vector(1 downto 0);
169 constant pwm_n: natural := 3; --number of pwm outputs
170 --number of ticks per pwm cycle, 2^11=2048
171 constant pwm_period : std_logic_vector (pwm_width-1 downto 0) := (others=>'1');
172 type pwm_res_type is array(1 to 3) of std_logic_vector (pwm_width-1 downto 0);
174 signal pwm_match: pwm_res_type; --point of reversion of pwm output, 0 to 2047
175 signal pwm_count: std_logic_vector (pwm_width-1 downto 0); --counter, 0 to 2047
176 signal pwm_sync: std_logic;
177 signal pwm_en_p: std_logic_vector(1 to 3);
178 signal pwm_en_n: std_logic_vector(1 to 3);
180 signal income_data_valid: std_logic;
182 signal clk_3M1: std_logic;
185 -- attribute syn_noprune of gpio2 : signal is true;
186 -- attribute syn_preserve of gpio2 : signal is true;
187 -- attribute syn_keep of gpio2 : signal is true;
188 -- attribute syn_hier of gpio2 : signal is true;
191 -- PLL as a reset generator
193 --zesileni signalu GPIO CLK
216 pwm_block: for i in pwm_n downto 1 generate
219 pwm_width => pwm_width
222 clock => gpio_clk, --50 Mhz clk from gpclk on raspberry
223 sync => pwm_sync, --counter restarts
224 data_valid => income_data_valid,
227 -- pwm config bits & match word
229 en_n => pwm_en_n(i), --enable positive pwm
230 en_p => pwm_en_p(i), --enable "negative" ->activate shutdown
231 match => pwm_match(i),
234 out_p => open,--pwm(i), --positive signal
235 out_n => open--shdn(i) --reverse signal is in shutdown mode
242 --reset => income_data_valid,
247 adc_reader_map: adc_reader
250 adc_reset => adc_reset,
251 adc_miso => adc_miso,
252 adc_channels => adc_channels,
253 adc_sclk => adc_sclk,
264 -- clka => pll_clkin,
265 -- gla => pll_clkout,
266 -- lock => pll_lock);
267 -- -- reset <= not pll_lock;
268 -- reset <= '0'; -- TODO: apply reset for good failsafe
272 dummy_unused <= gpio2 and gpio3 and gpio4 and
274 gpio12 and gpio13 and gpio14 and
275 gpio15 and gpio16 and gpio19 and
276 gpio20 and gpio21 and gpio26 and
277 stat(1) and stat(2) and stat(3) and
278 hal_in(1) and hal_in(2) and hal_in(3) and
279 irc_i and power_stat and
282 can_rx and can_tx and
283 dip_sw(1) and dip_sw(2) and dip_sw(3) and
285 gpio17 and gpio18 and gpio27 and gpio22 and gpio23 and gpio24 and gpio25 and
286 gpio8 and gpio11 and gpio7 and gpio10 and
287 ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
303 wait until (gpio_clk'event and gpio_clk='1');
304 IF(pwm_count = pwm_period) THEN
305 --end of period reached
306 pwm_count <= (others=>'0'); --reset counter
307 pwm_sync <= '1'; -- inform PWM logic about new period start
308 ELSE --end of period not reached
309 pwm_count <= std_logic_vector(unsigned(pwm_count)+1); --increment counter
316 --position is obtained on rising edge -> we should write it on next cycle
317 wait until (gpio_clk'event and gpio_clk='1');
319 --SCLK edge detection
320 spiclk_old(0)<=gpio11;
321 spiclk_old(1)<=spiclk_old(0);
325 ce0_old(1)<=ce0_old(0);
327 if (spiclk_old="01") then --rising edge, faze cteni
328 if (gpio7 = '0') then -- SPI CS must be selected
329 -- shift serial data into dat_reg on each rising edge
331 dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
333 elsif (spiclk_old="10" ) then --falling edge, faze zapisu
334 if (gpio7 = '0') then
335 gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB
340 --sestupna hrana SS, pripravime data pro prenos
341 if (ce0_old = "10" ) then
342 income_data_valid<='0';
343 dat_reg(95 downto 64) <= position(31 downto 0); --pozice
344 dat_reg(63 downto 61) <= hal_in(1 to 3); --halovy sondy
345 dat_reg(60 downto 36) <= (others => '1'); --let the rest fill with ones
346 dat_reg(35 downto 0) <= adc_channels(35 downto 0); --current mesurments
347 adc_reset<='0'; --remove reset flag, and wait on its rising edge
348 elsif (ce0_old = "01") then --rising edge of SS, we should read the data
349 adc_reset<=dat_reg(95);
350 pwm_en_p(1 to 3)<=dat_reg(94 downto 92);
351 pwm_en_n(1 to 3)<=dat_reg(91 downto 89);
352 --11 bit pwm TODO: make it generic
353 pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(34 downto 24);
354 pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(22 downto 12);
355 pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(10 downto 0);
356 income_data_valid<='1';