pmsm-control/adc_reader.vhdl

   1
   2
   3 library ieee;
   4 use ieee.std_logic_1164.all;
   5 use ieee.numeric_std.all;
   6 use work.util.all;
   7
   8 entity adc_reader is
   9 port (
  10         clk: in std_logic;                                      --input clk
  11         adc_reset: in std_logic;
  12         adc_miso: in std_logic;                                 --spi master in slave out
  13         adc_channels: out std_logic_vector (71 downto 0);       --consistent data of 3 channels
  14         adc_sclk: out std_logic;                                --spi clk
  15         adc_scs: out std_logic;                                 --spi slave select
  16         adc_mosi: out std_logic;                                --spi master out slave in
  17         measur_count: out std_logic_vector(8 downto 0)          --number of accumulated measurments
  18
  19 );
  20 end adc_reader;
  21
  22
  23 architecture behavioral of adc_reader is
  24
  25
  26         type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait);
  27         signal state : state_type;
  28
  29         type channel_type is (ch0, ch1, ch2);
  30
  31         signal adc_data: std_logic_vector(11 downto 0);
  32         signal adc_rst_old : std_logic_vector(1 downto 0);
  33         signal adc_address: std_logic_vector(2 downto 0);
  34         signal cumul_data: std_logic_vector(71 downto 0);       --unconsistent data, containing different amounts of measurments
  35         signal prepared_data: std_logic_vector(71 downto 0);    --consistent data, waiting for clk sync to propagate to output
  36         signal m_count_sig: std_logic_vector(8 downto 0);       --measurments count waiting for clk to propagate to output
  37         signal first_pass: std_logic;
  38 begin
  39
  40
  41         process
  42                 variable channel: channel_type;
  43                 variable reset_re: std_logic:='0';
  44                 variable reset_count: std_logic_vector (3 downto 0);
  45         begin
  46                 wait until (clk'event and clk='1');
  47
  48                 --rising edge detection of reset signal
  49                 adc_rst_old(0)<=adc_reset;
  50                 adc_rst_old(1)<=adc_rst_old(0);
  51
  52                 if (adc_rst_old="01") then
  53                         reset_re:='1';
  54                 end if;
  55
  56                 case state is
  57                         when reset=>
  58                                 reset_re:='0';                  --clear reset flag
  59                                 adc_scs<='1';                   --active-low SS
  60                                 adc_sclk<='0';                  --lower clock
  61                                 first_pass<='1';                --mark data as unprepared
  62                                 channel:=ch0;                   --prepare channel0
  63                                 adc_data<=(others=>'0');        --null working data
  64                                 cumul_data<=(others=>'0');      --null working data
  65                                 prepared_data<=(others=>'0');   --null the output
  66                                 adc_channels<=(others=>'0');    --null the output
  67                                 measur_count<=(others=>'0');    --null the count
  68                                 m_count_sig<=(others=>'0');     --null the count
  69                                 adc_address<="001";             --set its address
  70                                 reset_count:="0000";
  71                                 state<=rst_wait;
  72                         when rst_wait=>
  73                                 if (reset_count/="1111") then
  74                                         reset_count:=std_logic_vector(unsigned(reset_count)+1);
  75                                         --give the adc some time to prepare before transfer
  76                                         adc_scs<=not reset_count(3);
  77                                 else
  78                                         state<=f1;
  79                                 end if;
  80                         when f1=> --1st 'fallin edge' - its not falling edge in any case-if rst clock is low before
  81                                 adc_sclk<='0'; --clk
  82                                 adc_mosi<='1'; --start bit
  83                                 state<=r1; --next state
  84                         when r1=>       --1st rising edge (adc gets the start bit, we get date..)
  85                                 adc_sclk<='1';
  86                                 adc_data(5)<=adc_miso;
  87                                 state<=f2;
  88                         when f2=> --2nd falling edge
  89                                 adc_sclk<='0';
  90                                 adc_mosi<=adc_address(2); --A2 address
  91                                 state<=r2;
  92                         when r2=> --2nd rising edge (adc gets A2 address)
  93                                 adc_sclk<='1';
  94                                 adc_data(4)<=adc_miso;
  95                                 state<=f3;
  96                         when f3=> --3rd falling edge
  97                                 adc_sclk<='0';
  98                                 adc_mosi<=adc_address(1); --A1 address
  99                                 state<=r3;
 100                         when r3=> --rising edge
 101                                 adc_sclk<='1';
 102                                 adc_data(3)<=adc_miso;
 103                                 state<=f4;
 104                         when f4=> --4th falling edge
 105                                 adc_sclk<='0';
 106                                 adc_mosi<=adc_address(0); --A0 address
 107                                 state<=r4;
 108                         when r4=> --rising edge
 109                                 adc_sclk<='1';
 110                                 adc_data(2)<=adc_miso;
 111                                 state<=f5;
 112                         when f5=> --5th falling edge
 113                                 adc_sclk<='0';
 114                                 adc_mosi<='0'; --MODE (LOW -12bit)
 115                                 state<=r5;
 116                         when r5=> --rising edge
 117                                 adc_sclk<='1';
 118                                 adc_data(1)<=adc_miso;
 119                                 state<=f6;
 120                         when f6=> --6th falling edge
 121                                 adc_sclk<='0';
 122                                 adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
 123                                 state<=r6;
 124                         when r6=> --6th rising edge (we read last bit of conversion, adc gets SGL/DIF)
 125                                 adc_sclk<='1';
 126                                 adc_data(0)<=adc_miso;
 127                                 state<=f7;
 128                         when f7=> -- 7th falling edge
 129                                 adc_sclk<='0';
 130                                 adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
 131                                 state<=r7;
 132                         when r7=> --7th rising edge, data ready
 133                                 adc_sclk<='1';
 134                                 if (first_pass='0') then
 135                                         --add the current current to sum and shift the register
 136                                         cumul_data(71 downto 0)<=
 137                                                 std_logic_vector(unsigned(cumul_data(47 downto 24))
 138                                                         +unsigned(adc_data(11 downto 0)))
 139                                                 & cumul_data(23 downto 0)
 140                                                 & cumul_data(71 downto 48);
 141                                 end if;
 142                                 state<=f8;
 143                         when f8=> --8th falling edge
 144                                 adc_sclk<='0';
 145                                 adc_mosi<='0'; --PD0
 146                                 if (first_pass='0') then
 147                                         case channel is
 148                                                 when ch0=>
 149                                                         adc_address<="101";     --ch1 address
 150                                                         channel:=ch1;           --next channel code
 151                                                 when ch1=>
 152                                                         adc_address<="010";     --ch2 address
 153                                                         channel:=ch2;           --next channel code
 154                                                 when ch2=>
 155                                                         --data order schould be: ch2 downto ch0 downto ch1
 156                                                         prepared_data(71 downto 0)<=cumul_data(71 downto 0);
 157                                                         m_count_sig<=std_logic_vector(unsigned(m_count_sig)+1);
 158                                                         adc_address<="001";     --ch0 address
 159                                                         channel:=ch0;           --next channel code
 160                                         end case;
 161                                 end if;
 162                                 state<=r8;
 163                         when r8=> --8th rising edge (adc gets PD0), we propagate our results to output
 164                                 adc_sclk<='1';
 165                                 adc_channels <= prepared_data;          --data
 166                                 measur_count <= m_count_sig;            --count of measurments
 167                                 first_pass<='0';                        --data in next cycle are usable
 168                                 state<=f9;
 169                         when f9=> --9th falling edge busy state between conversion (we write nothing)
 170                                 adc_sclk<='0';
 171                                 state<=r9;
 172                         when r9=>  --9th rising edge (we nor ads get nothing)
 173                                 adc_sclk<='1';
 174                                 state<=f10;
 175                         when f10=> --10th falling edge
 176                                 adc_sclk<='0';
 177                                 state<=r10;
 178                         when r10=>  --10th rising edge (we read 1. bit of new conversion)
 179                                 adc_sclk<='1';
 180                                 adc_data(11)<=adc_miso;
 181                                 state<=f11;
 182                         when f11=>
 183                                 adc_sclk<='0';
 184                                 state<=r11;
 185                         when r11=>  --11th rising edge
 186                                 adc_sclk<='1';
 187                                 adc_data(10)<=adc_miso;
 188                                 state<=f12;
 189                         when f12=>
 190                                 adc_sclk<='0';
 191                                 state<=r12;
 192                         when r12=>  --12th rising edge
 193                                 adc_sclk<='1';
 194                                 adc_data(9)<=adc_miso;
 195                                 state<=f13;
 196                         when f13=>
 197                                 adc_sclk<='0';
 198                                 state<=r13;
 199                         when r13=>  --13th rising edge
 200                                 adc_sclk<='1';
 201                                 adc_data(8)<=adc_miso;
 202                                 state<=f14;
 203                         when f14=>
 204                                 adc_sclk<='0';
 205                                 state<=r14;
 206                         when r14=>  --14th rising edge
 207                                 adc_sclk<='1';
 208                                 adc_data(7)<=adc_miso;
 209                                 state<=f15;
 210                         when f15=>
 211                                 adc_sclk<='0';
 212                                 state<=r15;
 213                         when r15=> --15th rising edge
 214                                 adc_sclk<='1';
 215                                 adc_data(6)<=adc_miso;
 216                                 if (reset_re='1') then --we check rising edge of reset
 217                                         state<=reset;
 218                                 else
 219                                         state<=f1;
 220                                 end if;
 221                 end case;
 222         end process;
 223
 224
 225
 226 end behavioral;
 227