2 -- * LXPWR slave part *
3 -- common sioreg & common counter for several ADC&PWM blocks
5 -- part of LXPWR motion control board (c) PiKRON Ltd
6 -- idea by Pavel Pisa PiKRON Ltd <pisa@cmp.felk.cvut.cz>
7 -- code by Marek Peca <mp@duch.cz>
14 use ieee.std_logic_1164.all;
15 use ieee.numeric_std.all;
17 use work.qcounter.all;
19 entity rpi_mc_simple_dc is
21 gpio2: in std_logic; -- SDA
22 gpio3: in std_logic; -- SCL
23 gpio4: in std_logic; -- CLK
24 gpio14: in std_logic; -- Tx
25 gpio15: in std_logic; -- Rx
26 gpio17: out std_logic; -- RTS
27 gpio18: out std_logic; -- PWM0/PCMCLK
28 gpio27: out std_logic; -- SD1DAT3
29 gpio22: out std_logic; -- SD1CLK
30 gpio23: out std_logic; -- SD1CMD
31 gpio24: out std_logic; -- SD1DAT0
32 gpio10: in std_logic; -- SPI0MOSI
33 gpio9: out std_logic; -- SPI0MISO
34 gpio25: out std_logic; -- SD1DAT1
35 gpio11: in std_logic; -- SPI0SCLK
36 gpio8: in std_logic; -- SPI0CE0
37 gpio7: in std_logic; -- SPI0CE1
38 gpio5: in std_logic; -- GPCLK1
39 gpio6: in std_logic; -- GPCLK2
40 gpio12: in std_logic; -- PWM0
41 gpio13: in std_logic; -- PWM1
42 gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS
43 gpio16: in std_logic; -- SPI1CE2
44 gpio26: in std_logic; -- SD1DAT2
45 gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0
46 gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1
49 -- Each PWM signal has cooresponding shutdown
50 pwm: out std_logic_vector (1 to 3);
51 shdn: out std_logic_vector (1 to 3);
52 -- Fault/power stage status
53 stat: in std_logic_vector (1 to 3);
55 hal_in: in std_logic_vector (1 to 3);
61 power_stat: in std_logic;
63 adc_miso: in std_logic;
64 adc_mosi: in std_logic;
65 adc_sclk: in std_logic;
66 adc_scs: in std_logic;
68 ext_miso: in std_logic; --master in slave out
69 ext_mosi: in std_logic; --master out slave in
70 ext_sclk: in std_logic;
71 ext_scs0: in std_logic;
72 ext_scs1: in std_logic;
73 ext_scs2: in std_logic;
75 rs485_rxd: in std_logic;
76 rs485_txd: out std_logic;
77 rs485_dir: out std_logic;
82 dip_sw: in std_logic_vector (1 to 3); --na desce je prohozene cislovanni
83 -- Unused terminal to keep design tools silent
84 dummy_unused : out std_logic
89 architecture behavioral of rpi_mc_simple_dc is
90 attribute syn_noprune :boolean;
91 attribute syn_preserve :boolean;
92 attribute syn_keep :boolean;
93 attribute syn_hier :boolean;
95 -- component pll50to200
97 -- powerdown, clka: in std_logic;
98 -- lock, gla: out std_logic
103 port (A: in std_logic; Y: out std_logic);
110 a0, b0: in std_logic;
111 qcount: out std_logic_vector (31 downto 0);
112 a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
113 ab_error: out std_logic
117 signal spiclk_old_lvl: std_logic :='0'; --pro detekci hrany SPI hodin
118 signal pwm_in, pwm_dir_in: std_logic;
119 signal spi_clk: std_logic;
120 signal gpio_clk: std_logic;
121 signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); --registr pro SPI
122 signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
124 -- attribute syn_noprune of gpio2 : signal is true;
125 -- attribute syn_preserve of gpio2 : signal is true;
126 -- attribute syn_keep of gpio2 : signal is true;
127 -- attribute syn_hier of gpio2 : signal is true;
130 -- PLL as a reset generator
132 --zesileni signalu hodin SPI - bez zesileni nelze syntetizovat
139 --zesileni signalu GPIO CLK
165 -- clka => pll_clkin,
166 -- gla => pll_clkout,
167 -- lock => pll_lock);
168 -- -- reset <= not pll_lock;
169 -- reset <= '0'; -- TODO: apply reset for good failsafe
173 dummy_unused <= gpio2 and gpio3 and gpio4 and
175 gpio12 and gpio13 and gpio14 and
176 gpio15 and gpio16 and gpio19 and
177 gpio20 and gpio21 and gpio26 and
178 stat(1) and stat(2) and stat(3) and
179 hal_in(1) and hal_in(2) and hal_in(3) and
180 irc_i and power_stat and
181 adc_miso and adc_mosi and adc_sclk and adc_scs and
183 can_rx and can_tx and
184 dip_sw(1) and dip_sw(2) and dip_sw(3) and
186 -- gpio17 and gpio18 and gpio27 and gpio22 and
187 gpio8 and gpio11 and gpio7 and gpio10 and
188 ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
194 --gpio24 <= dip_sw(1); --na desce je prohozene cislovani
208 --if (gpio11'event and gpio11 = '1') then -- rising edge of SCK
209 if ((spi_clk = '1') and (spiclk_old_lvl = '0') ) then
210 if (gpio7 = '0') then -- SPI CS must be selected
211 -- shift serial data into dat_reg on each rising edge
213 dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
214 spiclk_old_lvl <= '1';
217 elsif ((spi_clk = '0') and (spiclk_old_lvl = '1')) then
218 if (gpio7 = '0') then
219 gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB
220 spiclk_old_lvl <= '0';