pmsm-control/rpi_mc_simple_dc.vhdl

   1 --
   2 -- * LXPWR slave part *
   3 --  common sioreg & common counter for several ADC&PWM blocks
   4 --
   5 -- part of LXPWR motion control board (c) PiKRON Ltd
   6 -- idea by Pavel Pisa PiKRON Ltd <pisa@cmp.felk.cvut.cz>
   7 -- code by Marek Peca <mp@duch.cz>
   8 -- 01/2013
   9 --
  10 -- license: GNU GPLv3
  11 --
  12
  13 library ieee;
  14 use ieee.std_logic_1164.all;
  15 use ieee.numeric_std.all;
  16 use work.util.all;
  17
  18 entity rpi_mc_simple_dc is
  19 port (
  20         gpio2: in std_logic; -- SDA
  21         gpio3: in std_logic; -- SCL
  22         gpio4: in std_logic; -- CLK
  23         gpio14: in std_logic; -- Tx
  24         gpio15: in std_logic; -- Rx
  25         gpio17: in std_logic; -- RTS
  26         gpio18: in std_logic; -- PWM0/PCMCLK
  27         gpio27: in std_logic; -- SD1DAT3
  28         gpio22: in std_logic; -- SD1CLK
  29         gpio23: in std_logic; -- SD1CMD
  30         gpio24: in std_logic; -- SD1DAT0
  31         gpio10: in std_logic; -- SPI0MOSI
  32         gpio9: out std_logic; -- SPI0MISO
  33         gpio25: in std_logic; -- SD1DAT1
  34         gpio11: in std_logic; -- SPI0SCLK
  35         gpio8: in std_logic; -- SPI0CE0
  36         gpio7: in std_logic; -- SPI0CE1
  37         gpio5: in std_logic; -- GPCLK1
  38         gpio6: in std_logic; -- GPCLK2
  39         gpio12: in std_logic; -- PWM0
  40         gpio13: in std_logic; -- PWM1
  41         gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS
  42         gpio16: in std_logic; -- SPI1CE2
  43         gpio26: in std_logic; -- SD1DAT2
  44         gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0
  45         gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1
  46         --
  47         -- PWM
  48         -- Each PWM signal has cooresponding shutdown
  49         pwm: out std_logic_vector (1 to 3);
  50         shdn: out std_logic_vector (1 to 3);
  51         -- Fault/power stage status
  52         stat: in std_logic_vector (1 to 3);
  53         -- HAL inputs
  54         hal_in: in std_logic_vector (1 to 3);
  55         -- IRC inputs
  56         irc_a: in std_logic;
  57         irc_b: in std_logic;
  58         irc_i: in std_logic;
  59         -- Power status
  60         power_stat: in std_logic;
  61         -- ADC for current
  62         adc_miso: in std_logic;
  63         adc_mosi: out std_logic;
  64         adc_sclk: out std_logic;
  65         adc_scs: out std_logic;
  66         -- Extarnal SPI
  67         ext_miso: in std_logic; --master in slave out
  68         ext_mosi: in std_logic; --master out slave in
  69         ext_sclk: in std_logic;
  70         ext_scs0: in std_logic;
  71         ext_scs1: in std_logic;
  72         ext_scs2: in std_logic;
  73         -- RS-485 Transceiver
  74         rs485_rxd: in std_logic;
  75         rs485_txd: out std_logic;
  76         rs485_dir: out std_logic;
  77         -- CAN Transceiver
  78         can_rx: in std_logic;
  79         can_tx: in std_logic;
  80         -- DIP switch
  81         dip_sw: in std_logic_vector (1 to 3); --na desce je prohozene cislovanni
  82         -- Unused terminal to keep design tools silent
  83         dummy_unused : out std_logic
  84 );
  85 end rpi_mc_simple_dc;
  86
  87
  88 architecture behavioral of rpi_mc_simple_dc is
  89         attribute syn_noprune :boolean;
  90         attribute syn_preserve :boolean;
  91         attribute syn_keep :boolean;
  92         attribute syn_hier :boolean;
  93         -- Actel lib
  94         -- component pll50to200
  95         --   port (
  96         --     powerdown, clka: in std_logic;
  97         --     lock, gla: out std_logic
  98         --   );
  99         -- end component;
 100
 101         component CLKINT
 102                 port (A: in std_logic; Y: out std_logic);
 103         end component;
 104
 105         component qcounter
 106         port (
 107                 clock: in std_logic;
 108                 reset: in std_logic;
 109                 a0, b0: in std_logic;
 110                 qcount: out std_logic_vector (31 downto 0);
 111                 a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
 112                 ab_error: out std_logic
 113         );
 114         end component;
 115
 116         type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,reset);
 117         signal state : state_type;
 118
 119         type channel_type is (ch0, ch1, ch2);
 120
 121         signal adc_data: std_logic_vector(11 downto 0); --ADC income data
 122         signal adc_reset : std_logic;
 123         signal adc_rst_old : std_logic_vector(1 downto 0);
 124         signal adc_address: std_logic_vector(8 downto 0);
 125         signal adc_channels: std_logic_vector(35 downto 0);
 126
 127         signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
 128         --signal pwm_in, pwm_dir_in: std_logic;
 129         signal gpio_clk: std_logic;
 130         signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
 131         signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
 132         signal ce0_old: std_logic_vector(1 downto 0);
 133
 134
 135
 136         --  attribute syn_noprune of gpio2 : signal is true;
 137         --  attribute syn_preserve of gpio2 : signal is true;
 138         --  attribute syn_keep of gpio2 : signal is true;
 139         --  attribute syn_hier of gpio2 : signal is true;
 140
 141 begin
 142         -- PLL as a reset generator
 143
 144         --zesileni signalu GPIO CLK
 145         copyclk2: CLKINT
 146         port map (
 147                 a => gpio4,
 148                 y => gpio_clk
 149         );
 150
 151
 152         qcount: qcounter
 153         port map (
 154                 clock => gpio_clk,
 155                 reset => '0',
 156                 a0 => irc_a,
 157                 b0 => irc_b,
 158                 qcount => position,
 159                 a_rise => open,
 160                 a_fall => open,
 161                 b_rise => open,
 162                 b_fall => open,
 163                 ab_event => open,
 164                 ab_error => open
 165         );
 166
 167
 168         --   pll: pll50to200
 169         --     port map (
 170         --       powerdown => '1',
 171         --       clka => pll_clkin,
 172         --       gla => pll_clkout,
 173         --       lock => pll_lock);
 174         -- --  reset <= not pll_lock;
 175         --   reset <= '0';                         -- TODO: apply reset for good failsafe
 176                                            -- upon power-on
 177         --   clock <= clkm;
 178
 179         dummy_unused <= gpio2 and gpio3  and gpio4 and
 180                 gpio5 and gpio6 and
 181                 gpio12 and gpio13 and gpio14 and
 182                 gpio15 and gpio16 and gpio19 and
 183                 gpio20 and gpio21 and gpio26 and
 184                 stat(1) and stat(2) and stat(3) and
 185                 hal_in(1) and hal_in(2) and hal_in(3) and
 186                 irc_i and power_stat and
 187                 adc_miso and
 188                 rs485_rxd and
 189                 can_rx and can_tx and
 190                 dip_sw(1) and dip_sw(2) and dip_sw(3) and
 191                 irc_a and irc_b and
 192                 gpio17 and gpio18 and gpio27 and gpio22 and gpio23 and gpio24 and gpio25 and
 193                 gpio8  and gpio11 and gpio7 and gpio10 and
 194                 ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
 195
 196         rs485_txd <= '1';
 197         rs485_dir <= '0';
 198
 199
 200         shdn(1) <= '0';
 201         shdn(2) <= '0';
 202         shdn(3) <= '1';
 203
 204         pwm(1) <= '0';
 205         pwm(2) <= '0';
 206         pwm(3) <= '0';
 207
 208
 209         process
 210         begin
 211                 --position is obtained on rising edge -> we should write it on next cycle
 212                 wait until (gpio_clk'event and gpio_clk='1');
 213
 214                 --SCLK edge detection
 215                 spiclk_old(0)<=gpio11;
 216                 spiclk_old(1)<=spiclk_old(0);
 217
 218                 --SS edge detection
 219                 ce0_old(0)<=gpio7;
 220                 ce0_old(1)<=ce0_old(0);
 221
 222                 if (spiclk_old="01") then --rising edge, faze cteni
 223                         if (gpio7 = '0') then             -- SPI CS must be selected
 224                                 -- shift serial data into dat_reg on each rising edge
 225                                 -- of SCK, MSB first
 226                                 dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
 227                                 end if;
 228                 elsif (spiclk_old="10" ) then --falling edge, faze zapisu
 229                         if (gpio7 = '0') then
 230                                 gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB
 231                         end if;
 232                 end if;
 233
 234
 235                 --sestupna hrana SS, pripravime data pro prenos
 236                 if (ce0_old = "10" ) then
 237                         dat_reg(95 downto 64) <= position(31 downto 0); --pozice
 238                         dat_reg(63 downto 61) <= hal_in(1 to 3); --halovy sondy
 239                         dat_reg(60 downto 36) <= (others => '1'); --let the rest fill with ones
 240                         dat_reg(35 downto 0) <= adc_channels(35 downto 0); --current mesurments
 241                 elsif (ce0_old = "01") then --rising edge of SS, we should read the data
 242                         adc_reset<=dat_reg(95);
 243                 end if;
 244         end process;
 245
 246         process
 247                 variable data_ready : std_logic;
 248                 variable channel: channel_type;
 249         begin
 250                 wait until (gpio_clk'event and gpio_clk='1');
 251                 case state is
 252                         when reset=>
 253                                 adc_scs<='1'; --active-high SS
 254                                 data_ready:='0';
 255                                 --addresse are CH(A2,A1,A0): CH0:(0,0,1),CH1:(1,0,1),CH2:(0,1,0)
 256                                 adc_address<="001101010";
 257                                 channel:=ch0;
 258                         when f1=>
 259                                 adc_scs<='0'; --active-high SS
 260                                 adc_sclk<='0'; --clk
 261                                 adc_mosi<='1'; --start bit
 262                                 state<=r1; --next state
 263                         when r1=>       --rising edge
 264                                 adc_sclk<='1';
 265                                 adc_data(5)<=adc_miso;
 266                                 state<=f2;
 267                         when f2=> --2nd falling edge
 268                                 adc_sclk<='0';
 269                                 adc_mosi<=adc_address(8); --A2 address
 270                                 state<=r2;
 271                         when r2=> --rising edge
 272                                 adc_sclk<='1';
 273                                 adc_data(4)<=adc_miso;
 274                                 state<=f3;
 275                         when f3=> --3rd falling edge
 276                                 adc_sclk<='0';
 277                                 adc_mosi<=adc_address(7); --A1 address
 278                                 state<=r3;
 279                         when r3=> --rising edge
 280                                 adc_sclk<='1';
 281                                 adc_data(3)<=adc_miso;
 282                                 state<=f4;
 283                         when f4=> --4th falling edge
 284                                 adc_sclk<='0';
 285                                 adc_mosi<=adc_address(6); --A0 address
 286                                 --shift the addresses
 287                                 adc_address(8 downto 0)<=adc_address(5 downto 0) & adc_address(8 downto 6);
 288                                 state<=r4;
 289                         when r4=> --rising edge
 290                                 adc_sclk<='1';
 291                                 adc_data(2)<=adc_miso;
 292                                 state<=f5;
 293                         when f5=> --5th falling edge
 294                                 adc_sclk<='0';
 295                                 adc_mosi<='0'; --MODE (LOW -12bit)
 296                                 state<=r5;
 297                         when r5=> --rising edge
 298                                 adc_sclk<='1';
 299                                 adc_data(1)<=adc_miso;
 300                                 state<=f6;
 301                         when f6=> --6th falling edge
 302                                 adc_sclk<='0';
 303                                 adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
 304                                 state<=r6;
 305                         when r6=> --rising edge
 306                                 adc_sclk<='1';
 307                                 adc_data(0)<=adc_miso;
 308                                 state<=f7;
 309                         when f7=> -- 7th falling edge
 310                                 adc_sclk<='0';
 311                                 adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
 312                                 state<=r7;
 313                         when r7=> --rising edge, data ready
 314                                 adc_sclk<='1';
 315                                 if (data_ready='1') then
 316                                         case channel is
 317                                                 when ch0=>
 318                                                         adc_channels(35 downto 24)<=adc_data(11 downto 0);
 319                                                         channel:=ch1;
 320                                                 when ch1=>
 321                                                         adc_channels(23 downto 12)<=adc_data(11 downto 0);
 322                                                         channel:=ch2;
 323                                                 when ch2=>
 324                                                         adc_channels(11 downto 0)<=adc_data(11 downto 0);
 325                                                         channel:=ch0;
 326                                         end case;
 327                                 end if;
 328                                 data_ready:='1';
 329                                 state<=f8;
 330                         when f8=> --8th falling edge
 331                                 adc_sclk<='0';
 332                                 adc_mosi<='0'; --PD0
 333                                 state<=r8;
 334                         when r8=> --rising edge
 335                                 adc_sclk<='1';
 336                                 state<=f9;
 337                         when f9=> --busy state between conversion, 9th falling edge
 338                                 adc_sclk<='0';
 339                                 state<=r9;
 340                         when r9=>  --10th rising edge
 341                                 adc_sclk<='1';
 342                                 adc_data(11)<=adc_miso;
 343                                 state<=f10;
 344                         when f10=>
 345                                 adc_sclk<='0';
 346                                 state<=r10;
 347                         when r10=>  --11th rising edge
 348                                 adc_sclk<='1';
 349                                 adc_data(10)<=adc_miso;
 350                                 state<=f11;
 351                         when f11=>
 352                                 adc_sclk<='0';
 353                                 state<=r11;
 354                         when r11=>  --12th rising edge
 355                                 adc_sclk<='1';
 356                                 adc_data(9)<=adc_miso;
 357                                 state<=f12;
 358                         when f12=>
 359                                 adc_sclk<='0';
 360                                 state<=r12;
 361                         when r12=>  --13th rising edge
 362                                 adc_sclk<='1';
 363                                 adc_data(8)<=adc_miso;
 364                                 state<=f13;
 365                         when f13=>
 366                                 adc_sclk<='0';
 367                                 state<=r13;
 368                         when r13=>  --14th rising edge
 369                                 adc_sclk<='1';
 370                                 adc_data(7)<=adc_miso;
 371                                 state<=f14;
 372                         when f14=>
 373                                 adc_sclk<='0';
 374                                 --for rising edge detection in next cycle
 375                                 adc_rst_old(0)<=adc_reset;
 376                                 adc_rst_old(1)<=adc_rst_old(0);
 377                                 state<=r14;
 378                         when r14=> --15th rising edge
 379                                 adc_sclk<='1';
 380                                 adc_data(6)<=adc_miso;
 381                                 if (adc_rst_old="01") then --we check rising edge of reset
 382                                         state<=reset;
 383                                 else
 384                                         state<=f1;
 385                                 end if;
 386                 end case;
 387         end process;
 388
 389
 390
 391 end behavioral;
 392