pmsm-control/par.tcl

   1 # designer SCRIPT:par.tcl LOGFILE:par.log
   2
   3 # create a new design
   4 new_design -name "rpi_mc_simple_dc" -family "IGLOO"
   5
   6 set_device \
   7     -die AGL125V5 \
   8     -package "100 VQFP" \
   9     -speed STD \
  10     -voltage 1.5 \
  11     -iostd LVTTL \
  12     -jtag yes \
  13     -probe yes \
  14     -trst yes \
  15     -temprange COM \
  16     -voltrange COM
  17
  18 # set default back-annotation base-name
  19 set_defvar "BA_NAME" "rpi_mc_simple_dc_ba"
  20
  21 # set working directory
  22 set_defvar "DESDIR" "par0"
  23
  24 # set back-annotation output directory
  25 set_defvar "BA_DIR" "par0"
  26
  27 # enable the export back-annotation netlist
  28 set_defvar "BA_NETLIST_ALSO" "1"
  29
  30 # setup status report options
  31 set_defvar "EXPORT_STATUS_REPORT" "1"
  32 set_defvar "EXPORT_STATUS_REPORT_FILENAME" "rpi_mc_simple_dc.rpt"
  33
  34 # legacy audit-mode flags (left here for historical reasons)
  35 set_defvar "AUDIT_NETLIST_FILE" "1"
  36 set_defvar "AUDIT_DCF_FILE" "1"
  37 set_defvar "AUDIT_PIN_FILE" "1"
  38 set_defvar "AUDIT_ADL_FILE" "1"
  39
  40 # import of input files
  41 import_source  \
  42 -format "edif" -edif_flavor "GENERIC" -netlist_naming "VHDL" "syn0/rpi_mc_simple_dc.edn" \
  43 -format "pdc" "rpi_mc_1.pdc"
  44
  45 # export translation of original netlist
  46 export -format "vhdl" "_map.vhdl"
  47
  48 compile \
  49     -pdc_abort_on_error on \
  50     -pdc_eco_display_unmatched_objects off \
  51     -pdc_eco_max_warnings 10000 \
  52     -demote_globals off \
  53     -demote_globals_max_fanout 12 \
  54     -promote_globals off \
  55     -promote_globals_min_fanout 200 \
  56     -promote_globals_max_limit 0 \
  57     -localclock_max_shared_instances 12 \
  58     -localclock_buffer_tree_max_fanout 12 \
  59     -combine_register on \
  60     -delete_buffer_tree off \
  61     -delete_buffer_tree_max_fanout 12 \
  62     -report_high_fanout_nets_limit 10
  63
  64 # auxiliary source files
  65 import_aux -format "sdc" "syn0/rpi_mc_simple_dc_sdc.sdc"
  66
  67 save_design rpi_mc_simple_dc.adb
  68
  69 layout \
  70     -timing_driven \
  71     -run_placer on \
  72     -place_incremental off \
  73     -run_router on \
  74     -route_incremental off \
  75     -placer_high_effort off
  76
  77 save_design rpi_mc_simple_dc.adb
  78
  79 export \
  80     -format bts_stp \
  81     -feature prog_fpga \
  82     rpi_mc_simple_dc.stp
  83
  84 save_design rpi_mc_simple_dc.adb