pmsm-control/divider.vhdl

   1 -- provides frequency division by 12
   2 -- initialy intended to make 4.17Mhz from 50Mhz
   3
   4 library ieee;
   5 use ieee.std_logic_1164.all;
   6 use ieee.numeric_std.all;
   7 use work.util.all;
   8
   9 entity divider is
  10
  11 port (
  12         clk_in: in std_logic;
  13         div12: out std_logic
  14 );
  15 end divider;
  16
  17
  18 architecture behavioral of divider is
  19         signal count : std_logic_vector (2 downto 0);
  20         signal tmp : std_logic;
  21 begin
  22
  23
  24         divider : process
  25         begin
  26                 wait until (clk_in'event and clk_in='1');
  27                 if (count(2 downto 1)="11") then
  28                         count<="000";
  29                         tmp <= not tmp;
  30                 else
  31                         count <= std_logic_vector(unsigned(count) + 1);
  32                 end if;
  33                         div12<=tmp;
  34     end process divider;
  35
  36
  37
  38 end behavioral;
  39