pmsm-control/adc_reader.vhdl

   1 --
   2 -- * Raspberry Pi BLDC/PMSM motor control design for RPi-MI-1 board *
   3 -- SPI connected multichannel current ADC read and averaging
   4 --
   5 -- (c) 2015 Martin Prudek <prudemar@fel.cvut.cz>
   6 -- Czech Technical University in Prague
   7 --
   8 -- Project supervision and original project idea
   9 -- idea by Pavel Pisa <pisa@cmp.felk.cvut.cz>
  10 --
  11 -- Related RPi-MI-1 hardware is designed by Petr Porazil,
  12 -- PiKRON Ltd  <http://www.pikron.com>
  13 --
  14 -- license: GNU LGPL and GPLv3+
  15 --
  16
  17 library ieee;
  18 use ieee.std_logic_1164.all;
  19 use ieee.numeric_std.all;
  20 use work.util.all;
  21
  22 entity adc_reader is
  23 port (
  24         clk: in std_logic;                                      --synchronous master clk
  25         divided_clk : in std_logic;                             --divided clk - value suitable to sourcing voltage
  26         adc_reset: in std_logic;                                --synchronous reset on rising edge
  27
  28         adc_miso: in std_logic;                                 --spi master in slave out
  29         adc_sclk: out std_logic;                                --spi clk
  30         adc_scs: out std_logic;                                 --spi slave select
  31         adc_mosi: out std_logic;                                --spi master out slave in
  32
  33         adc_channels: out std_logic_vector (71 downto 0);       --consistent data of 3 channels
  34         measur_count: out std_logic_vector(8 downto 0)          --number of accumulated measurments
  35
  36 );
  37 end adc_reader;
  38
  39
  40 architecture behavioral of adc_reader is
  41
  42
  43         type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait);
  44         signal state : state_type;
  45
  46         type channel_type is (ch0, ch1, ch2);
  47
  48         signal adc_data: std_logic_vector(11 downto 0);
  49         signal adc_rst_prev : std_logic;
  50         signal adc_address: std_logic_vector(2 downto 0);
  51         signal cumul_data: std_logic_vector(71 downto 0);       --unconsistent data, containing different amounts of measurments
  52         signal prepared_data: std_logic_vector(71 downto 0);    --consistent data, waiting for clk sync to propagate to output
  53         signal m_count_sig: std_logic_vector(8 downto 0);       --measurments count waiting for clk to propagate to output
  54         signal first_pass: std_logic;
  55         signal div_clk_prev: std_logic;
  56 begin
  57
  58
  59         process
  60                 variable channel: channel_type;
  61                 variable reset_re: std_logic:='0';
  62                 variable reset_count: std_logic_vector (3 downto 0);
  63         begin
  64                 wait until (clk'event and clk='1');
  65
  66                 --rising edge detection of reset signal
  67                 adc_rst_prev<=adc_reset;
  68                 if (adc_rst_prev='0') and (adc_reset='1') then
  69                         reset_re:='1';
  70                 end if;
  71
  72                 --rising edge detection of divided clk signal
  73                 div_clk_prev<=divided_clk;
  74                 if (divided_clk='1') and (div_clk_prev='0') then
  75
  76                 case state is
  77                         when reset=>
  78                                 reset_re:='0';                  --clear reset flag
  79                                 adc_scs<='1';                   --active-low SS
  80                                 adc_sclk<='0';                  --lower clock
  81                                 first_pass<='1';                --mark data as unprepared
  82                                 channel:=ch0;                   --prepare channel0
  83                                 adc_data<=(others=>'0');        --null working data
  84                                 cumul_data<=(others=>'0');      --null working data
  85                                 prepared_data<=(others=>'0');   --null the output
  86                                 adc_channels<=(others=>'0');    --null the output
  87                                 measur_count<=(others=>'0');    --null the count
  88                                 m_count_sig<=(others=>'0');     --null the count
  89                                 adc_address<="001";             --set its address
  90                                 reset_count:="0000";
  91                                 state<=rst_wait;
  92                         when rst_wait=>
  93                                 if (reset_count/="1111") then
  94                                         reset_count:=std_logic_vector(unsigned(reset_count)+1);
  95                                         --give the adc some time to prepare before transfer
  96                                         adc_scs<=not reset_count(3);
  97                                 else
  98                                         state<=f1;
  99                                 end if;
 100                         when f1=> --1st 'fallin edge' - its not falling edge in any case-if rst clock is low before
 101                                 adc_sclk<='0'; --clk
 102                                 adc_mosi<='1'; --start bit
 103                                 state<=r1; --next state
 104                         when r1=>       --1st rising edge (adc gets the start bit, we get date..)
 105                                 adc_sclk<='1';
 106                                 adc_data(5)<=adc_miso;
 107                                 state<=f2;
 108                         when f2=> --2nd falling edge
 109                                 adc_sclk<='0';
 110                                 adc_mosi<=adc_address(2); --A2 address
 111                                 state<=r2;
 112                         when r2=> --2nd rising edge (adc gets A2 address)
 113                                 adc_sclk<='1';
 114                                 adc_data(4)<=adc_miso;
 115                                 state<=f3;
 116                         when f3=> --3rd falling edge
 117                                 adc_sclk<='0';
 118                                 adc_mosi<=adc_address(1); --A1 address
 119                                 state<=r3;
 120                         when r3=> --rising edge
 121                                 adc_sclk<='1';
 122                                 adc_data(3)<=adc_miso;
 123                                 state<=f4;
 124                         when f4=> --4th falling edge
 125                                 adc_sclk<='0';
 126                                 adc_mosi<=adc_address(0); --A0 address
 127                                 state<=r4;
 128                         when r4=> --rising edge
 129                                 adc_sclk<='1';
 130                                 adc_data(2)<=adc_miso;
 131                                 state<=f5;
 132                         when f5=> --5th falling edge
 133                                 adc_sclk<='0';
 134                                 adc_mosi<='0'; --MODE (LOW -12bit)
 135                                 state<=r5;
 136                         when r5=> --rising edge
 137                                 adc_sclk<='1';
 138                                 adc_data(1)<=adc_miso;
 139                                 state<=f6;
 140                         when f6=> --6th falling edge
 141                                 adc_sclk<='0';
 142                                 adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
 143                                 state<=r6;
 144                         when r6=> --6th rising edge (we read last bit of conversion, adc gets SGL/DIF)
 145                                 adc_sclk<='1';
 146                                 adc_data(0)<=adc_miso;
 147                                 state<=f7;
 148                         when f7=> -- 7th falling edge
 149                                 adc_sclk<='0';
 150                                 adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
 151                                 state<=r7;
 152                         when r7=> --7th rising edge, data ready
 153                                 adc_sclk<='1';
 154                                 if (first_pass='0') then
 155                                         --add the current current to sum and shift the register
 156                                         cumul_data(71 downto 0)<=
 157                                                 std_logic_vector(unsigned(cumul_data(47 downto 24))
 158                                                         +unsigned(adc_data(11 downto 0)))
 159                                                 & cumul_data(23 downto 0)
 160                                                 & cumul_data(71 downto 48);
 161                                 end if;
 162                                 state<=f8;
 163                         when f8=> --8th falling edge
 164                                 adc_sclk<='0';
 165                                 adc_mosi<='0'; --PD0
 166                                 if (first_pass='0') then
 167                                         case channel is
 168                                                 when ch0=>
 169                                                         adc_address<="101";     --ch1 address
 170                                                         channel:=ch1;           --next channel code
 171                                                 when ch1=>
 172                                                         adc_address<="010";     --ch2 address
 173                                                         channel:=ch2;           --next channel code
 174                                                 when ch2=>
 175                                                         --data order schould be: ch2 downto ch0 downto ch1
 176                                                         prepared_data(71 downto 0)<=cumul_data(71 downto 0);
 177                                                         m_count_sig<=std_logic_vector(unsigned(m_count_sig)+1);
 178                                                         adc_address<="001";     --ch0 address
 179                                                         channel:=ch0;           --next channel code
 180                                         end case;
 181                                 end if;
 182                                 state<=r8;
 183                         when r8=> --8th rising edge (adc gets PD0), we propagate our results to output
 184                                 adc_sclk<='1';
 185                                 adc_channels <= prepared_data;          --data
 186                                 measur_count <= m_count_sig;            --count of measurments
 187                                 first_pass<='0';                        --data in next cycle are usable
 188                                 state<=f9;
 189                         when f9=> --9th falling edge busy state between conversion (we write nothing)
 190                                 adc_sclk<='0';
 191                                 state<=r9;
 192                         when r9=>  --9th rising edge (we nor ads get nothing)
 193                                 adc_sclk<='1';
 194                                 state<=f10;
 195                         when f10=> --10th falling edge
 196                                 adc_sclk<='0';
 197                                 state<=r10;
 198                         when r10=>  --10th rising edge (we read 1. bit of new conversion)
 199                                 adc_sclk<='1';
 200                                 adc_data(11)<=adc_miso;
 201                                 state<=f11;
 202                         when f11=>
 203                                 adc_sclk<='0';
 204                                 state<=r11;
 205                         when r11=>  --11th rising edge
 206                                 adc_sclk<='1';
 207                                 adc_data(10)<=adc_miso;
 208                                 state<=f12;
 209                         when f12=>
 210                                 adc_sclk<='0';
 211                                 state<=r12;
 212                         when r12=>  --12th rising edge
 213                                 adc_sclk<='1';
 214                                 adc_data(9)<=adc_miso;
 215                                 state<=f13;
 216                         when f13=>
 217                                 adc_sclk<='0';
 218                                 state<=r13;
 219                         when r13=>  --13th rising edge
 220                                 adc_sclk<='1';
 221                                 adc_data(8)<=adc_miso;
 222                                 state<=f14;
 223                         when f14=>
 224                                 adc_sclk<='0';
 225                                 state<=r14;
 226                         when r14=>  --14th rising edge
 227                                 adc_sclk<='1';
 228                                 adc_data(7)<=adc_miso;
 229                                 state<=f15;
 230                         when f15=>
 231                                 adc_sclk<='0';
 232                                 state<=r15;
 233                         when r15=> --15th rising edge
 234                                 adc_sclk<='1';
 235                                 adc_data(6)<=adc_miso;
 236                                 if (reset_re='1') then --we check rising edge of reset
 237                                         state<=reset;
 238                                 else
 239                                         state<=f1;
 240                                 end if;
 241                 end case;
 242
 243                 end if;
 244
 245         end process;
 246
 247
 248
 249 end behavioral;
 250