ADC reader moved to separate file.
[fpga/rpi-motor-control.git] / pmsm-control / adc_reader.vhdl
1
2
3 library ieee;
4 use ieee.std_logic_1164.all;
5 use ieee.numeric_std.all;
6 use work.util.all;
7
8 entity adc_reader is
9 port (
10         clk: in std_logic;                                      --input clk
11         adc_reset: in std_logic;
12         adc_miso: in std_logic;                                 --spi master in slave out
13         adc_channels: out std_logic_vector (35 downto 0);       --consistent data of 3 channels
14         adc_sclk: out std_logic;                                --spi clk
15         adc_scs: out std_logic;                                 --spi slave select
16         adc_mosi: out std_logic                                 --spi master out slave in
17         
18 );
19 end adc_reader;
20
21
22 architecture behavioral of adc_reader is
23         
24         
25         type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait);
26         signal state : state_type;
27         
28         type channel_type is (ch0, ch1, ch2);
29         
30         signal adc_data: std_logic_vector(11 downto 0); 
31         signal adc_rst_old : std_logic_vector(1 downto 0);
32         signal adc_address: std_logic_vector(8 downto 0);
33         
34 begin
35         
36         
37         process 
38                 variable data_ready : std_logic;
39                 variable channel: channel_type;
40                 variable reset_re: std_logic:='0';
41                 variable reset_count: integer:=0;
42         begin
43                 wait until (clk'event and clk='1');
44                 
45                 --reset rising edge detection
46                 adc_rst_old(0)<=adc_reset;
47                 adc_rst_old(1)<=adc_rst_old(0);
48                 
49                 if (adc_rst_old="01") then
50                         reset_re:='1';
51                 end if;
52                 
53                 case state is
54                         when reset=>
55                                 reset_re:='0'; --clear reset flag
56                                 adc_scs<='1'; --active-low SS
57                                 adc_sclk<='0'; --lower clock
58                                 data_ready:='0'; 
59                                 --addresse are CH(A2,A1,A0): CH0:(0,0,1),CH1:(1,0,1),CH2:(0,1,0)
60                                 adc_address<="001101010";
61                                 channel:=ch0;
62                                 adc_channels(35 downto 0)<=(others=>'1'); --for debug only - remove this line!
63                                 adc_data(11 downto 0)<=(others=>'1');
64                                 reset_count:=0;
65                                 state<=rst_wait;
66                         when rst_wait=>
67                                 if (reset_count<10) then
68                                         reset_count:=reset_count+1;
69                                         if (reset_count=7) then
70                                                 adc_scs<='0'; --give the adc some time to prepare before trensfer
71                                         end if;
72                                 else
73                                         state<=f1;
74                                 end if;
75                         when f1=> --1st 'fallin edge' - its not falling edge in any case-if rst clock is low before  
76                                 adc_sclk<='0'; --clk
77                                 adc_mosi<='1'; --start bit
78                                 state<=r1; --next state
79                         when r1=>       --1st rising edge (adc gets the start bit, we get date..)
80                                 adc_sclk<='1'; 
81                                 adc_data(5)<=adc_miso;
82                                 state<=f2;
83                         when f2=> --2nd falling edge
84                                 adc_sclk<='0';
85                                 adc_mosi<=adc_address(8); --A2 address
86                                 state<=r2;
87                         when r2=> --2nd rising edge (adc gets A2 address)
88                                 adc_sclk<='1';
89                                 adc_data(4)<=adc_miso;
90                                 state<=f3;
91                         when f3=> --3rd falling edge 
92                                 adc_sclk<='0';
93                                 adc_mosi<=adc_address(7); --A1 address
94                                 state<=r3;
95                         when r3=> --rising edge
96                                 adc_sclk<='1';
97                                 adc_data(3)<=adc_miso;
98                                 state<=f4;      
99                         when f4=> --4th falling edge
100                                 adc_sclk<='0';
101                                 adc_mosi<=adc_address(6); --A0 address
102                                 --shift the addresses
103                                 adc_address(8 downto 0)<=adc_address(5 downto 0) & adc_address(8 downto 6); 
104                                 state<=r4;
105                         when r4=> --rising edge
106                                 adc_sclk<='1';
107                                 adc_data(2)<=adc_miso;
108                                 state<=f5;      
109                         when f5=> --5th falling edge
110                                 adc_sclk<='0';
111                                 adc_mosi<='0'; --MODE (LOW -12bit)
112                                 state<=r5;
113                         when r5=> --rising edge
114                                 adc_sclk<='1';
115                                 adc_data(1)<=adc_miso;
116                                 state<=f6;      
117                         when f6=> --6th falling edge
118                                 adc_sclk<='0';
119                                 adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
120                                 state<=r6;
121                         when r6=> --6th rising edge (we read last bit of conversion, adc gets SGL/DIF)
122                                 adc_sclk<='1';
123                                 adc_data(0)<=adc_miso;
124                                 state<=f7;              
125                         when f7=> -- 7th falling edge
126                                 adc_sclk<='0';
127                                 adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
128                                 state<=r7;
129                         when r7=> --7th rising edge, data ready
130                                 adc_sclk<='1';
131                                 if (data_ready='1') then
132                                         case channel is
133                                                 when ch0=>
134                                                         adc_channels(35 downto 24)<=adc_data(11 downto 0);
135                                                         --adc_channels(35 downto 24)<=(others=>'0');
136                                                         channel:=ch1;
137                                                 when ch1=>
138                                                         adc_channels(23 downto 12)<=adc_data(11 downto 0);
139                                                         --adc_channels(23 downto 12)<=(others=>'1');
140                                                         channel:=ch2;
141                                                 when ch2=>
142                                                         adc_channels(11 downto 0)<=adc_data(11 downto 0);
143                                                         --adc_channels(11 downto 0)<=(others=>'0');
144                                                         channel:=ch0;
145                                         end case;
146                                 end if;
147                                 data_ready:='1';
148                                 state<=f8;      
149                         when f8=> --8th falling edge
150                                 adc_sclk<='0';
151                                 adc_mosi<='0'; --PD0
152                                 state<=r8;
153                         when r8=> --8th rising edge (adc gets PD0)
154                                 adc_sclk<='1';
155                                 state<=f9;
156                         when f9=> --9th falling edge busy state between conversion (we write nothing)
157                                 adc_sclk<='0';
158                                 state<=r9;
159                         when r9=>  --9th rising edge (we nor ads get nothing)
160                                 adc_sclk<='1';
161                                 state<=f10;
162                         when f10=> --10th falling edge
163                                 adc_sclk<='0';
164                                 state<=r10;
165                         when r10=>  --10th rising edge (we read 1. bit of conversion)
166                                 adc_sclk<='1';
167                                 adc_data(11)<=adc_miso;
168                                 state<=f11;
169                         when f11=>
170                                 adc_sclk<='0';
171                                 state<=r11;
172                         when r11=>  --11th rising edge
173                                 adc_sclk<='1';
174                                 adc_data(10)<=adc_miso;
175                                 state<=f12;
176                         when f12=>
177                                 adc_sclk<='0';
178                                 state<=r12;
179                         when r12=>  --12th rising edge
180                                 adc_sclk<='1';
181                                 adc_data(9)<=adc_miso;
182                                 state<=f13;
183                         when f13=>
184                                 adc_sclk<='0';
185                                 state<=r13;
186                         when r13=>  --13th rising edge
187                                 adc_sclk<='1';
188                                 adc_data(8)<=adc_miso;
189                                 state<=f14;
190                         when f14=>
191                                 adc_sclk<='0';
192                                 state<=r14;
193                         when r14=>  --14th rising edge
194                                 adc_sclk<='1';
195                                 adc_data(7)<=adc_miso;
196                                 state<=f15;
197                         when f15=>
198                                 adc_sclk<='0';
199                                 --for rising edge detection in next cycle
200                                 state<=r15;
201                         when r15=> --15th rising edge
202                                 adc_sclk<='1';
203                                 adc_data(6)<=adc_miso;
204                                 if (reset_re='1') then --we check rising edge of reset 
205                                         state<=reset;
206                                 else
207                                         state<=f1;
208                                 end if;
209                 end case;
210         end process;
211                         
212         
213                 
214 end behavioral;
215