4 use ieee.std_logic_1164.all;
5 use ieee.numeric_std.all;
10 clk: in std_logic; --input clk
11 adc_reset: in std_logic;
12 adc_miso: in std_logic; --spi master in slave out
13 adc_channels: out std_logic_vector (35 downto 0); --consistent data of 3 channels
14 adc_sclk: out std_logic; --spi clk
15 adc_scs: out std_logic; --spi slave select
16 adc_mosi: out std_logic --spi master out slave in
22 architecture behavioral of adc_reader is
25 type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait);
26 signal state : state_type;
28 type channel_type is (ch0, ch1, ch2);
30 signal adc_data: std_logic_vector(11 downto 0);
31 signal adc_rst_old : std_logic_vector(1 downto 0);
32 signal adc_address: std_logic_vector(8 downto 0);
38 variable data_ready : std_logic;
39 variable channel: channel_type;
40 variable reset_re: std_logic:='0';
41 variable reset_count: integer:=0;
43 wait until (clk'event and clk='1');
45 --reset rising edge detection
46 adc_rst_old(0)<=adc_reset;
47 adc_rst_old(1)<=adc_rst_old(0);
49 if (adc_rst_old="01") then
55 reset_re:='0'; --clear reset flag
56 adc_scs<='1'; --active-low SS
57 adc_sclk<='0'; --lower clock
59 --addresse are CH(A2,A1,A0): CH0:(0,0,1),CH1:(1,0,1),CH2:(0,1,0)
60 adc_address<="001101010";
62 adc_channels(35 downto 0)<=(others=>'1'); --for debug only - remove this line!
63 adc_data(11 downto 0)<=(others=>'1');
67 if (reset_count<10) then
68 reset_count:=reset_count+1;
69 if (reset_count=7) then
70 adc_scs<='0'; --give the adc some time to prepare before trensfer
75 when f1=> --1st 'fallin edge' - its not falling edge in any case-if rst clock is low before
77 adc_mosi<='1'; --start bit
78 state<=r1; --next state
79 when r1=> --1st rising edge (adc gets the start bit, we get date..)
81 adc_data(5)<=adc_miso;
83 when f2=> --2nd falling edge
85 adc_mosi<=adc_address(8); --A2 address
87 when r2=> --2nd rising edge (adc gets A2 address)
89 adc_data(4)<=adc_miso;
91 when f3=> --3rd falling edge
93 adc_mosi<=adc_address(7); --A1 address
95 when r3=> --rising edge
97 adc_data(3)<=adc_miso;
99 when f4=> --4th falling edge
101 adc_mosi<=adc_address(6); --A0 address
102 --shift the addresses
103 adc_address(8 downto 0)<=adc_address(5 downto 0) & adc_address(8 downto 6);
105 when r4=> --rising edge
107 adc_data(2)<=adc_miso;
109 when f5=> --5th falling edge
111 adc_mosi<='0'; --MODE (LOW -12bit)
113 when r5=> --rising edge
115 adc_data(1)<=adc_miso;
117 when f6=> --6th falling edge
119 adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
121 when r6=> --6th rising edge (we read last bit of conversion, adc gets SGL/DIF)
123 adc_data(0)<=adc_miso;
125 when f7=> -- 7th falling edge
127 adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
129 when r7=> --7th rising edge, data ready
131 if (data_ready='1') then
134 adc_channels(35 downto 24)<=adc_data(11 downto 0);
135 --adc_channels(35 downto 24)<=(others=>'0');
138 adc_channels(23 downto 12)<=adc_data(11 downto 0);
139 --adc_channels(23 downto 12)<=(others=>'1');
142 adc_channels(11 downto 0)<=adc_data(11 downto 0);
143 --adc_channels(11 downto 0)<=(others=>'0');
149 when f8=> --8th falling edge
153 when r8=> --8th rising edge (adc gets PD0)
156 when f9=> --9th falling edge busy state between conversion (we write nothing)
159 when r9=> --9th rising edge (we nor ads get nothing)
162 when f10=> --10th falling edge
165 when r10=> --10th rising edge (we read 1. bit of conversion)
167 adc_data(11)<=adc_miso;
172 when r11=> --11th rising edge
174 adc_data(10)<=adc_miso;
179 when r12=> --12th rising edge
181 adc_data(9)<=adc_miso;
186 when r13=> --13th rising edge
188 adc_data(8)<=adc_miso;
193 when r14=> --14th rising edge
195 adc_data(7)<=adc_miso;
199 --for rising edge detection in next cycle
201 when r15=> --15th rising edge
203 adc_data(6)<=adc_miso;
204 if (reset_re='1') then --we check rising edge of reset