2 -- * Raspberry Pi BLDC/PMSM motor control design for RPi-MC-1 board *
3 -- SPI connected multichannel current ADC read and averaging
5 -- (c) 2015 Martin Prudek <prudemar@fel.cvut.cz>
6 -- Czech Technical University in Prague
8 -- Project supervision and original project idea
9 -- idea by Pavel Pisa <pisa@cmp.felk.cvut.cz>
11 -- Related RPi-MC-1 hardware is designed by Petr Porazil,
12 -- PiKRON Ltd <http://www.pikron.com>
14 -- license: GNU LGPL and GPLv3+
18 use ieee.std_logic_1164.all;
19 use ieee.numeric_std.all;
24 clk: in std_logic; --input clk
25 adc_reset: in std_logic;
26 adc_miso: in std_logic; --spi master in slave out
27 adc_channels: out std_logic_vector (71 downto 0); --consistent data of 3 channels
28 adc_sclk: out std_logic; --spi clk
29 adc_scs: out std_logic; --spi slave select
30 adc_mosi: out std_logic; --spi master out slave in
31 measur_count: out std_logic_vector(8 downto 0) --number of accumulated measurments
37 architecture behavioral of adc_reader is
40 type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait);
41 signal state : state_type;
43 type channel_type is (ch0, ch1, ch2);
45 signal adc_data: std_logic_vector(11 downto 0);
46 signal adc_rst_old : std_logic_vector(1 downto 0);
47 signal adc_address: std_logic_vector(2 downto 0);
48 signal cumul_data: std_logic_vector(71 downto 0); --unconsistent data, containing different amounts of measurments
49 signal prepared_data: std_logic_vector(71 downto 0); --consistent data, waiting for clk sync to propagate to output
50 signal m_count_sig: std_logic_vector(8 downto 0); --measurments count waiting for clk to propagate to output
51 signal first_pass: std_logic;
56 variable channel: channel_type;
57 variable reset_re: std_logic:='0';
58 variable reset_count: std_logic_vector (3 downto 0);
60 wait until (clk'event and clk='1');
62 --rising edge detection of reset signal
63 adc_rst_old(0)<=adc_reset;
64 adc_rst_old(1)<=adc_rst_old(0);
66 if (adc_rst_old="01") then
72 reset_re:='0'; --clear reset flag
73 adc_scs<='1'; --active-low SS
74 adc_sclk<='0'; --lower clock
75 first_pass<='1'; --mark data as unprepared
76 channel:=ch0; --prepare channel0
77 adc_data<=(others=>'0'); --null working data
78 cumul_data<=(others=>'0'); --null working data
79 prepared_data<=(others=>'0'); --null the output
80 adc_channels<=(others=>'0'); --null the output
81 measur_count<=(others=>'0'); --null the count
82 m_count_sig<=(others=>'0'); --null the count
83 adc_address<="001"; --set its address
87 if (reset_count/="1111") then
88 reset_count:=std_logic_vector(unsigned(reset_count)+1);
89 --give the adc some time to prepare before transfer
90 adc_scs<=not reset_count(3);
94 when f1=> --1st 'fallin edge' - its not falling edge in any case-if rst clock is low before
96 adc_mosi<='1'; --start bit
97 state<=r1; --next state
98 when r1=> --1st rising edge (adc gets the start bit, we get date..)
100 adc_data(5)<=adc_miso;
102 when f2=> --2nd falling edge
104 adc_mosi<=adc_address(2); --A2 address
106 when r2=> --2nd rising edge (adc gets A2 address)
108 adc_data(4)<=adc_miso;
110 when f3=> --3rd falling edge
112 adc_mosi<=adc_address(1); --A1 address
114 when r3=> --rising edge
116 adc_data(3)<=adc_miso;
118 when f4=> --4th falling edge
120 adc_mosi<=adc_address(0); --A0 address
122 when r4=> --rising edge
124 adc_data(2)<=adc_miso;
126 when f5=> --5th falling edge
128 adc_mosi<='0'; --MODE (LOW -12bit)
130 when r5=> --rising edge
132 adc_data(1)<=adc_miso;
134 when f6=> --6th falling edge
136 adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
138 when r6=> --6th rising edge (we read last bit of conversion, adc gets SGL/DIF)
140 adc_data(0)<=adc_miso;
142 when f7=> -- 7th falling edge
144 adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
146 when r7=> --7th rising edge, data ready
148 if (first_pass='0') then
149 --add the current current to sum and shift the register
150 cumul_data(71 downto 0)<=
151 std_logic_vector(unsigned(cumul_data(47 downto 24))
152 +unsigned(adc_data(11 downto 0)))
153 & cumul_data(23 downto 0)
154 & cumul_data(71 downto 48);
157 when f8=> --8th falling edge
160 if (first_pass='0') then
163 adc_address<="101"; --ch1 address
164 channel:=ch1; --next channel code
166 adc_address<="010"; --ch2 address
167 channel:=ch2; --next channel code
169 --data order schould be: ch2 downto ch0 downto ch1
170 prepared_data(71 downto 0)<=cumul_data(71 downto 0);
171 m_count_sig<=std_logic_vector(unsigned(m_count_sig)+1);
172 adc_address<="001"; --ch0 address
173 channel:=ch0; --next channel code
177 when r8=> --8th rising edge (adc gets PD0), we propagate our results to output
179 adc_channels <= prepared_data; --data
180 measur_count <= m_count_sig; --count of measurments
181 first_pass<='0'; --data in next cycle are usable
183 when f9=> --9th falling edge busy state between conversion (we write nothing)
186 when r9=> --9th rising edge (we nor ads get nothing)
189 when f10=> --10th falling edge
192 when r10=> --10th rising edge (we read 1. bit of new conversion)
194 adc_data(11)<=adc_miso;
199 when r11=> --11th rising edge
201 adc_data(10)<=adc_miso;
206 when r12=> --12th rising edge
208 adc_data(9)<=adc_miso;
213 when r13=> --13th rising edge
215 adc_data(8)<=adc_miso;
220 when r14=> --14th rising edge
222 adc_data(7)<=adc_miso;
227 when r15=> --15th rising edge
229 adc_data(6)<=adc_miso;
230 if (reset_re='1') then --we check rising edge of reset