Added UNTESTED version of spi-commands-lost detection.
FIX: dff3.vhdl added to syn.tcl.
Simple frequency divider replaced with more complex counter.
Include SDC Synopsys Design Constraints file to the design file lists. This file allows fine definition of clocks relations and parameters. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
Modified ADC clk frequency from 3.2 MHz to 2.08Mhz
Project renamed 'to rpi_pmsm_control'.
ADC reader moved to separate file.
GPCLK frequency from RPi increased from 2Mhz to 50Mhz. To keep clk frequency for ADC lower then 3.2Mhz, freqency divider(divides by 8) have been added.
Integration of mcpwm into toplevel entity.
qcounter.vhdl and dff.vhdl added to syn.tcl
pridan podadresar pmsm-control