1 #ifndef _ZYNQ_3PMDRV1_MC_H
2 #define _ZYNQ_3PMDRV1_MC_H
6 #define Z3PMDRV1_CHAN_COUNT 3
8 #define Z3PMDRV1_PWM_VALUE_m 0x0ffff
9 #define Z3PMDRV1_PWM_ENABLE 0x10000
10 #define Z3PMDRV1_PWM_SHUTDOWN 0x20000
12 typedef struct z3pmdrv1_state_t {
13 uintptr_t regs_base_phys;
15 uint32_t pwm[Z3PMDRV1_CHAN_COUNT];
20 int32_t curadc_val[Z3PMDRV1_CHAN_COUNT];
21 int32_t curadc_offs[Z3PMDRV1_CHAN_COUNT];
24 uint16_t curadc_sqn_last;
25 uint32_t curadc_cumsum[Z3PMDRV1_CHAN_COUNT];
26 uint32_t curadc_cumsum_last[Z3PMDRV1_CHAN_COUNT];
29 int z3pmdrv1_init(z3pmdrv1_state_t *z3pmcst);
31 int z3pmdrv1_transfer(z3pmdrv1_state_t *z3pmcst);
33 #endif /*_ZYNQ_3PMDRV1_MC_H*/