From ca161152c478d97b2dd53a8a7e0ad5287ef6ed12 Mon Sep 17 00:00:00 2001
From: Marek Peca <mp@duch.cz>
Date: Mon, 18 Oct 2010 14:38:04 +0200
Subject: [PATCH] + Makefile, DFF for input synchronization, ab carry corrected

---
 Makefile      | 16 ++++++++++++++++
 dff.vhdl      | 26 ++++++++++++++++++++++++++
 qcounter.vhdl | 31 ++++++++++++++++++++++++++-----
 3 files changed, 68 insertions(+), 5 deletions(-)
 create mode 100644 Makefile
 create mode 100644 dff.vhdl

diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..0a1a454
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,16 @@
+VHDL_MAIN=qctest
+VHDL_SUB=dff.o qcounter.o
+
+all: $(VHDL_MAIN)
+
+run: $(VHDL_MAIN)
+	ghdl -r $< --stop-time=8us --vcd=$<.vcd
+
+$(VHDL_MAIN): $(VHDL_MAIN).o $(VHDL_SUB)
+	ghdl -e --ieee=synopsys $@
+
+%.o: %.vhdl
+	ghdl -a --ieee=synopsys $<
+
+clean:
+	rm -Rf *.o qctest
diff --git a/dff.vhdl b/dff.vhdl
new file mode 100644
index 0000000..c703058
--- /dev/null
+++ b/dff.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity dff is
+  port (
+    clock: in std_logic;
+    d: in std_logic;
+    q: out std_logic
+  );
+end dff;
+
+architecture behavioral of dff is
+  signal data: std_logic := '0';
+begin
+  q <= data;
+
+  process
+  begin
+    wait until clock'event and clock = '1';
+    data <= d;
+  end process;
+
+end behavioral;
diff --git a/qcounter.vhdl b/qcounter.vhdl
index 90f6b05..e4abbd6 100644
--- a/qcounter.vhdl
+++ b/qcounter.vhdl
@@ -8,7 +8,7 @@ entity qcounter is
   port (
     clock: in std_logic;
     reset: in std_logic;
-    a, b: in std_logic;
+    a0, b0: in std_logic;
     qcount: out std_logic_vector (31 downto 0);
     a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
     ab_error: out std_logic
@@ -16,12 +16,33 @@ entity qcounter is
 end qcounter;
 
 architecture behavioral of qcounter is
-  subtype std_logic4 is std_logic_vector (3 downto 0);
-  signal a_prev, b_prev: std_logic;
+  component dff
+    port (
+      clock: in std_logic;
+      d: in std_logic;
+      q: out std_logic
+    );
+  end component;
+
+subtype std_logic4 is std_logic_vector (3 downto 0);
+  signal a, b, a_prev, b_prev: std_logic;
   signal count: std_logic_vector (29 downto 0)
     := "000000000000000000000000000000";
   signal count_next: std_logic_vector (29 downto 0);
 begin
+  dff_a: dff
+    port map (
+      clock => clock,
+      d => a0,
+      q => a
+    );
+  dff_b: dff
+    port map (
+      clock => clock,
+      d => b0,
+      q => b
+    );
+  
   qcount(0) <= a_prev xor b_prev;
   qcount(1) <= b_prev;
   qcount(31 downto 2) <= count;
@@ -48,9 +69,9 @@ begin
 
   comb_count: process (a_prev, b_prev, a, b, count)
   begin
-    if (a_prev = '1') and (b_prev = '0') and (a = '0') and (b = '0') then
+    if (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
       count_next <= count + 1;
-    elsif (a_prev = '0') and (b_prev = '0') and (a = '1') and (b = '0') then
+    elsif (a_prev = '0') and (b_prev = '0') and (a = '0') and (b = '1') then
       count_next <= count - 1;
     else
       count_next <= count;
-- 
2.39.2