From: Marek Peca <mp@duch.cz>
Date: Tue, 2 Nov 2010 10:25:30 +0000 (+0100)
Subject: qcount output moved one clock ahead (now consistent with event signals)
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/quadcount.git/commitdiff_plain/ea76c5b4cb4f4f829fab147501a0811b1c7b7eb5

qcount output moved one clock ahead (now consistent with event signals)
---

diff --git a/qcounter.vhdl b/qcounter.vhdl
index e4abbd6..2984614 100644
--- a/qcounter.vhdl
+++ b/qcounter.vhdl
@@ -26,9 +26,9 @@ architecture behavioral of qcounter is
 
 subtype std_logic4 is std_logic_vector (3 downto 0);
   signal a, b, a_prev, b_prev: std_logic;
-  signal count: std_logic_vector (29 downto 0)
+  signal count_prev: std_logic_vector (29 downto 0)
     := "000000000000000000000000000000";
-  signal count_next: std_logic_vector (29 downto 0);
+  signal count: std_logic_vector (29 downto 0);
 begin
   dff_a: dff
     port map (
@@ -43,8 +43,8 @@ begin
       q => b
     );
   
-  qcount(0) <= a_prev xor b_prev;
-  qcount(1) <= b_prev;
+  qcount(0) <= a xor b;
+  qcount(1) <= b;
   qcount(31 downto 2) <= count;
   
   comb_event: process (a_prev, b_prev, a, b)
@@ -70,11 +70,11 @@ begin
   comb_count: process (a_prev, b_prev, a, b, count)
   begin
     if (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
-      count_next <= count + 1;
+      count <= count_prev + 1;
     elsif (a_prev = '0') and (b_prev = '0') and (a = '0') and (b = '1') then
-      count_next <= count - 1;
+      count <= count_prev - 1;
     else
-      count_next <= count;
+      count <= count_prev;
     end if;
   end process;
 
@@ -82,9 +82,9 @@ begin
   begin
     wait until clock'event and clock = '1';
     if reset = '1' then
-      count <= "000000000000000000000000000000";
+      count_prev <= "000000000000000000000000000000";
     else
-      count <= count_next;
+      count_prev <= count;
     end if;
     a_prev <= a;
     b_prev <= b;