+ Makefile, DFF for input synchronization, ab carry corrected

[fpga/quadcount.git] / qcounter.vhdl

diff --git a/qcounter.vhdl b/qcounter.vhdl
index 90f6b056d6e8f83a88237e2ae0e0820834199b68..e4abbd60ad11d393f8826bf37e00ee37a2144f49 100644 (file)
--- a/qcounter.vhdl
+++ b/qcounter.vhdl
@@ -8,7 +8,7 @@ entity qcounter is
   port (
     clock: in std_logic;
     reset: in std_logic;
-    a, b: in std_logic;
+    a0, b0: in std_logic;
     qcount: out std_logic_vector (31 downto 0);
     a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
     ab_error: out std_logic
@@ -16,12 +16,33 @@ entity qcounter is
 end qcounter;
 
 architecture behavioral of qcounter is
-  subtype std_logic4 is std_logic_vector (3 downto 0);
-  signal a_prev, b_prev: std_logic;
+  component dff
+    port (
+      clock: in std_logic;
+      d: in std_logic;
+      q: out std_logic
+    );
+  end component;
+
+subtype std_logic4 is std_logic_vector (3 downto 0);
+  signal a, b, a_prev, b_prev: std_logic;
   signal count: std_logic_vector (29 downto 0)
     := "000000000000000000000000000000";
   signal count_next: std_logic_vector (29 downto 0);
 begin
+  dff_a: dff
+    port map (
+      clock => clock,
+      d => a0,
+      q => a
+    );
+  dff_b: dff
+    port map (
+      clock => clock,
+      d => b0,
+      q => b
+    );
+  
   qcount(0) <= a_prev xor b_prev;
   qcount(1) <= b_prev;
   qcount(31 downto 2) <= count;
@@ -48,9 +69,9 @@ begin
 
   comb_count: process (a_prev, b_prev, a, b, count)
   begin
-    if (a_prev = '1') and (b_prev = '0') and (a = '0') and (b = '0') then
+    if (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
       count_next <= count + 1;
-    elsif (a_prev = '0') and (b_prev = '0') and (a = '1') and (b = '0') then
+    elsif (a_prev = '0') and (b_prev = '0') and (a = '0') and (b = '1') then
       count_next <= count - 1;
     else
       count_next <= count;