subtype std_logic4 is std_logic_vector (3 downto 0);
signal a, b, a_prev, b_prev: std_logic;
- signal count: std_logic_vector (29 downto 0)
+ signal count_prev: std_logic_vector (29 downto 0)
:= "000000000000000000000000000000";
- signal count_next: std_logic_vector (29 downto 0);
+ signal count: std_logic_vector (29 downto 0);
begin
dff_a: dff
port map (
q => b
);
- qcount(0) <= a_prev xor b_prev;
- qcount(1) <= b_prev;
+ qcount(0) <= a xor b;
+ qcount(1) <= b;
qcount(31 downto 2) <= count;
comb_event: process (a_prev, b_prev, a, b)
comb_count: process (a_prev, b_prev, a, b, count)
begin
if (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
- count_next <= count + 1;
+ count <= count_prev + 1;
elsif (a_prev = '0') and (b_prev = '0') and (a = '0') and (b = '1') then
- count_next <= count - 1;
+ count <= count_prev - 1;
else
- count_next <= count;
+ count <= count_prev;
end if;
end process;
begin
wait until clock'event and clock = '1';
if reset = '1' then
- count <= "000000000000000000000000000000";
+ count_prev <= "000000000000000000000000000000";
else
- count <= count_next;
+ count_prev <= count;
end if;
a_prev <= a;
b_prev <= b;