library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity quadcount_tb is
end quadcount_tb;

architecture behavioral of quadcount_tb is
  component qcounter
    port (
      clock: in std_logic;
      reset: in std_logic;
      a, b: in std_logic;
      qcount: out std_logic_vector (31 downto 0);
      a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
      ab_error: out std_logic
    );
  end component;

  signal clock, reset, a, b: std_logic;
begin
  qc0: qcounter
    port map (
      clock => clock,
      reset => reset,
      a => a,
      b => b
    );

  reset <= '0';
  a <= '0';
  b <= '0';
  
  test: process
  begin
    clock <= '0';
    wait for 1 us;
    clock <= '1';
    wait for 1 us;
  end process;
end behavioral;