rtime.felk.cvut.cz Git - fpga/pwm.git/tree

]> rtime.felk.cvut.cz Git - fpga/pwm.git/tree

projects / fpga / pwm.git / tree

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-rw-r--r--	1596	counter.vhd	blob \| history \| raw
-rw-r--r--	606	gen_sin_lut.m	blob \| history \| raw
-rw-r--r--	4289	mcc.vhd	blob \| history \| raw
-rw-r--r--	3908	mcc_master.vhd	blob \| history \| raw
-rw-r--r--	927	priority_encoder.vhd	blob \| history \| raw
-rw-r--r--	2723	pwm.vhd	blob \| history \| raw
-rw-r--r--	5632	sin.lut	blob \| history \| raw
drwxr-xr-x	-	tb	tree \| history
-rw-r--r--	3757	vector_gen.vhd	blob \| history \| raw
-rw-r--r--	2515	wave_table.vhd	blob \| history \| raw

The control block for three phases BLDC motor PWM output with profile based commutation logic