From cbc8cf4054dcd685e213504704a132b13d1b57c1 Mon Sep 17 00:00:00 2001 From: Vladimir Burian Date: Thu, 24 Mar 2011 11:59:41 +0100 Subject: [PATCH] PWM_dump added to the MCC a its test bench. --- mcc.vhd | 79 ++++++++++++++++++++++++++++++++++++++++++++------- tb/Makefile | 7 +++++ tb/tb_mcc.sav | 20 ++++++++----- tb/tb_mcc.vhd | 32 ++++++++++----------- 4 files changed, 105 insertions(+), 33 deletions(-) diff --git a/mcc.vhd b/mcc.vhd index 2e0ab55..2bda9c9 100644 --- a/mcc.vhd +++ b/mcc.vhd @@ -40,9 +40,12 @@ end entity mcc; architecture behavioral of mcc is - constant MCC_W : integer := 5; - constant MUX_W : integer := 2; + constant MCC_W : integer := 6; + constant MUX_W : integer := 3; + constant P_BASE : integer := 16; + constant P_SIZE : integer := 4; + signal MCC_ACK : std_logic_vector (MCC_W-1 downto 0); signal MCC_STB : std_logic_vector (MCC_W-1 downto 0); @@ -59,6 +62,17 @@ architecture behavioral of mcc is signal VECTOR_IRF_STB_O : std_logic; signal VECTOR_IRF_WE_O : std_logic; + signal PWM_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0); + signal PWM_IRF_DAT_O : std_logic_vector (15 downto 0); + signal PWM_IRF_STB_O : std_logic; + --signal PWM_DAT_O : std_logic_vector (LUT_DAT_W-1 downto 0); + signal PWM_STB_O : std_logic; + signal PWM_SL_ACK_O : std_logic; + signal PWM_SL_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0); + signal PWM_SL_STB_I : std_logic; + signal PWM_SL_MUX_CODE : std_logic_vector (1 downto 0); + + type state_t is (ready, read_mask, do_mcc, done); @@ -75,21 +89,29 @@ architecture behavioral of mcc is begin IRF_ADR_O <= MASTER_IRF_ADR_O when MCC_MUX_EN = '0' else - VECTOR_IRF_ADR_O when MCC_MUX_CODE = 1 else + VECTOR_IRF_ADR_O when MCC_MUX_CODE = 2 else + PWM_IRF_ADR_O when MCC_MUX_CODE = 5 else (others => '-'); IRF_DAT_O <= MASTER_IRF_DAT_O when MCC_MUX_EN = '0' else - VECTOR_IRF_DAT_O when MCC_MUX_CODE = 1 else + VECTOR_IRF_DAT_O when MCC_MUX_CODE = 2 else + PWM_IRF_DAT_O when MCC_MUX_CODE = 5 else (others => '-'); IRF_STB_O <= MASTER_IRF_STB_O when MCC_MUX_EN = '0' else - VECTOR_IRF_STB_O when MCC_MUX_CODE = 1 else + VECTOR_IRF_STB_O when MCC_MUX_CODE = 2 else + PWM_IRF_STB_O when MCC_MUX_CODE = 5 else '0'; IRF_WE_O <= MASTER_IRF_WE_O when MCC_MUX_EN = '0' else - VECTOR_IRF_WE_O when MCC_MUX_CODE = 1 else + VECTOR_IRF_WE_O when MCC_MUX_CODE = 2 else '0'; + + PWM1_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 0 else '0'; + PWM2_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 1 else '0'; + PWM3_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 2 else '0'; + mcc_master_1 : entity work.mcc_master generic map ( @@ -114,13 +136,16 @@ begin vector_gen_1 : entity work.vector_gen generic map ( - A_BASE => 1, - P_BASE => 2) + A_BASE => 16#04#, + P_BASE => 16#10#, + P1_OFF => 16#01#, + P2_OFF => 16#05#, + P3_OFF => 16#09#) port map ( - ACK_O => MCC_ACK (1), + ACK_O => MCC_ACK (2), CLK_I => CLK_I, RST_I => RST_I, - STB_I => MCC_STB (1), + STB_I => MCC_STB (2), IRF_ACK_I => IRF_ACK_I, IRF_ADR_O => VECTOR_IRF_ADR_O, IRF_CYC_O => open, @@ -132,5 +157,39 @@ begin LUT_DAT_I => LUT_DAT_I, LUT_STB_O => LUT_STB_O); + pwm_dump_sequencer : entity work.sequencer + generic map ( + IRF_ADR_W => IRF_ADR_W, + P_BASE => P_BASE, + P_SIZE => P_SIZE) + port map ( + ACK_O => MCC_ACK (5), + CLK_I => CLK_I, + RST_I => RST_I, + STB_I => MCC_STB (5), + IRF_ADR_O => PWM_IRF_ADR_O, + SL_ACK_I => PWM_SL_ACK_O, + SL_IRF_ADR_I => PWM_SL_IRF_ADR_O, + SL_STB_O => PWM_SL_STB_I, + SL_MUX_CODE => PWM_SL_MUX_CODE); + + pwm_dump_1 : entity work.pwm_dump + generic map ( + IRF_ADR_W => IRF_ADR_W, + P_BASE => P_BASE, + PWM_OFF => 1, + PWM_W => LUT_DAT_W) + port map ( + ACK_O => PWM_SL_ACK_O, + CLK_I => CLK_I, + RST_I => RST_I, + STB_I => PWM_SL_STB_I, + PWM_DAT_O => PWM_DAT_O, + PWM_STB_O => PWM_STB_O, + IRF_ACK_I => IRF_ACK_I, + IRF_ADR_O => PWM_SL_IRF_ADR_O, + IRF_DAT_I => IRF_DAT_I, + IRF_STB_O => PWM_IRF_STB_O); + end architecture behavioral; diff --git a/tb/Makefile b/tb/Makefile index 5ceb879..0dfbf20 100644 --- a/tb/Makefile +++ b/tb/Makefile @@ -1,3 +1,7 @@ +# Be aware of required VHDL_ENTITIES sequence! All entities must be listed in +# bottom to up order (e.g. the top entity is the last in this list). Otherwise +# it won't compile. + VHDL_MAIN = tb_mcc VHDL_ENTITIES = counter.o \ pwm.o \ @@ -5,8 +9,11 @@ VHDL_ENTITIES = counter.o \ vector_gen.o \ priority_encoder.o \ mcc_master.o \ + sequencer.o \ + pwm_dump.o \ mcc.o + STOP_TIME = 50us diff --git a/tb/tb_mcc.sav b/tb/tb_mcc.sav index 627764b..f805787 100644 --- a/tb/tb_mcc.sav +++ b/tb/tb_mcc.sav @@ -1,18 +1,24 @@ [timestart] 0 [size] 1280 746 [pos] -1 -1 -*-33.327084 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-33.443600 14600000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] uut. +[treeopen] uut.mcc_master_1. @28 clk_i rst_i stb_i ack_o -@29 -dbg_mem0[15:0] +dbg_mem00[15:0] @22 -dbg_mem1[15:0] -dbg_mem2[15:0] -dbg_mem3[15:0] -dbg_mem4[15:0] +dbg_mem04[15:0] +dbg_mem11[15:0] +dbg_mem15[15:0] +dbg_mem19[15:0] +uut.pwm_dat_o[9:0] +@28 +uut.pwm1_stb_o +uut.pwm2_stb_o +uut.pwm3_stb_o [pattern_trace] 1 [pattern_trace] 0 diff --git a/tb/tb_mcc.vhd b/tb/tb_mcc.vhd index 738cc10..03d7059 100644 --- a/tb/tb_mcc.vhd +++ b/tb/tb_mcc.vhd @@ -10,7 +10,7 @@ end tb_mcc; architecture testbench of tb_mcc is - constant period : time := 1 us; + constant period : time := 500 ns; constant offset : time := 0 us; constant LUT_DAT_W : integer := 10; @@ -41,12 +41,12 @@ architecture testbench of tb_mcc is subtype word_t is std_logic_vector (15 downto 0); - signal dbg_mem0 : word_t := "0000000000000010"; -- read only by mcc_master - signal dbg_mem1 : word_t := (others => '0'); -- read only by vector_gen - signal dbg_mem2 : word_t := (others => '0'); - signal dbg_mem3 : word_t := (others => '0'); - signal dbg_mem4 : word_t := (others => '0'); - signal dbg_ack : std_logic := '0'; + signal dbg_mem00 : word_t := "0000000000100100"; -- MCC enable flags (RO) + signal dbg_mem04 : word_t := (others => '0'); -- Angle (RO) + signal dbg_mem11 : word_t := (others => '0'); -- Phase 1 + signal dbg_mem15 : word_t := (others => '0'); -- Phase 2 + signal dbg_mem19 : word_t := (others => '0'); -- Phase 3 + signal dbg_ack : std_logic := '0'; -------------------------------------------------------------------------------- @@ -127,18 +127,18 @@ begin if rising_edge(CLK_I) and IRF_STB_O = '1' then if IRF_WE_O = '0' then case conv_integer(IRF_ADR_O) is - when 0 => IRF_DAT_I <= dbg_mem0; - when 1 => IRF_DAT_I <= dbg_mem1; - when 2 => IRF_DAT_I <= dbg_mem2; - when 3 => IRF_DAT_I <= dbg_mem3; - when 4 => IRF_DAT_I <= dbg_mem4; + when 16#00# => IRF_DAT_I <= dbg_mem00; + when 16#04# => IRF_DAT_I <= dbg_mem04; + when 16#11# => IRF_DAT_I <= dbg_mem11; + when 16#15# => IRF_DAT_I <= dbg_mem15; + when 16#19# => IRF_DAT_I <= dbg_mem19; when others => IRF_DAT_I <= (others => '0'); end case; else case conv_integer(IRF_ADR_O) is - when 2 => dbg_mem2 <= IRF_DAT_O; - when 3 => dbg_mem3 <= IRF_DAT_O; - when 4 => dbg_mem4 <= IRF_DAT_O; + when 16#11# => dbg_mem11 <= IRF_DAT_O; + when 16#15# => dbg_mem15 <= IRF_DAT_O; + when 16#19# => dbg_mem19 <= IRF_DAT_O; when others => null; end case; end if; @@ -155,7 +155,7 @@ begin wait for 4*period; for i in 0 to 1 loop - dbg_mem1 <= conv_std_logic_vector(i, 16); + dbg_mem04 <= conv_std_logic_vector(i, 16); STB_I <= '1'; wait until rising_edge(CLK_I) and ACK_O = '1'; -- 2.39.2