X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/pwm.git/blobdiff_plain/42a170534dd5885e961c9208fb615f7a7403deee..7c10fab4d2484fd07ed396ea5cd5407e48f90fb8:/mcc.vhd

diff --git a/mcc.vhd b/mcc.vhd
index e2ddc90..0002339 100644
--- a/mcc.vhd
+++ b/mcc.vhd
@@ -74,6 +74,11 @@ architecture behavioral of mcc is
   signal SCALE_SL_ACK_O     : std_logic;
   signal SCALE_SL_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
   signal SCALE_SL_STB_I     : std_logic;
+
+  signal PMIN_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+  signal PMIN_IRF_DAT_O : std_logic_vector (15 downto 0);
+  signal PMIN_IRF_STB_O : std_logic;
+  signal PMIN_IRF_WE_O  : std_logic;
   
   signal PWM_IRF_ADR_O    : std_logic_vector (IRF_ADR_W-1 downto 0);
   signal PWM_IRF_STB_O    : std_logic;
@@ -114,6 +119,7 @@ begin
                BASE_IRF_ADR_O   when MCC_MUX_CODE = 1 else
                VECTOR_IRF_ADR_O when MCC_MUX_CODE = 2 else
                SCALE_IRF_ADR_O  when MCC_MUX_CODE = 3 else
+               PMIN_IRF_ADR_O   when MCC_MUX_CODE = 4 else
                PWM_IRF_ADR_O    when MCC_MUX_CODE = 5 else
                (others => 'X');
 
@@ -122,6 +128,7 @@ begin
                BASE_IRF_DAT_O   when MCC_MUX_CODE = 1 else
                VECTOR_IRF_DAT_O when MCC_MUX_CODE = 2 else
                SCALE_IRF_DAT_O  when MCC_MUX_CODE = 3 else
+               PMIN_IRF_DAT_O   when MCC_MUX_CODE = 4 else
                (others => 'X');
 
   IRF_STB_O <= MASTER_IRF_STB_O when MCC_MUX_EN = '0' else
@@ -129,6 +136,7 @@ begin
                BASE_IRF_STB_O   when MCC_MUX_CODE = 1 else
                VECTOR_IRF_STB_O when MCC_MUX_CODE = 2 else
                SCALE_IRF_STB_O  when MCC_MUX_CODE = 3 else
+               PMIN_IRF_STB_O   when MCC_MUX_CODE = 4 else
                PWM_IRF_STB_O    when MCC_MUX_CODE = 5 else
                '0';
 
@@ -137,6 +145,7 @@ begin
               BASE_IRF_WE_O   when MCC_MUX_CODE = 1 else
               VECTOR_IRF_WE_O when MCC_MUX_CODE = 2 else
               SCALE_IRF_WE_O  when MCC_MUX_CODE = 3 else
+              PMIN_IRF_WE_O   when MCC_MUX_CODE = 4 else
               '0';
 
 
@@ -144,7 +153,6 @@ begin
   PWM2_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 1 else '0';
   PWM3_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 2 else '0';
 
-  MCC_ACK (4) <= '1';
 
   
   mcc_master_1 : entity work.mcc_master
@@ -280,6 +288,26 @@ begin
       IRF_STB_O => SCALE_IRF_STB_O,
       IRF_WE_O  => SCALE_IRF_WE_O);
 
+  pwm_min_1 : entity work.pwm_min
+    generic map (
+      IRF_ADR_W  => IRF_ADR_W,
+      PWM_W      => LUT_DAT_W,
+      BASE       => 0,
+      PWMMIN_OFF => 6,
+      P_BASE     => P_BASE,
+      P_SIZE     => P_SIZE,
+      PWM_OFF    => 1)
+    port map (
+      ACK_O     => MCC_ACK (4),
+      CLK_I     => CLK_I,
+      RST_I     => RST_I,
+      STB_I     => MCC_STB (4),
+      IRF_ACK_I => IRF_ACK_I,
+      IRF_ADR_O => PMIN_IRF_ADR_O,
+      IRF_DAT_I => IRF_DAT_I,
+      IRF_DAT_O => PMIN_IRF_DAT_O,
+      IRF_STB_O => PMIN_IRF_STB_O,
+      IRF_WE_O  => PMIN_IRF_WE_O);
   
   pwm_dump_sequencer : entity work.sequencer
     generic map (
@@ -297,12 +325,14 @@ begin
       SL_STB_O     => PWM_SL_STB_I,
       SL_MUX_CODE  => PWM_SL_MUX_CODE);
 
-  pwm_dump_1 : entity work.pwm_dump
+  pwm_min_dump_1 : entity work.pwm_min_dump
     generic map (
-      IRF_ADR_W => IRF_ADR_W,
-      P_BASE    => P_BASE,
-      PWM_OFF   => 1,
-      PWM_W     => LUT_DAT_W)
+      IRF_ADR_W  => IRF_ADR_W,
+      BASE       => 0,
+      PWMMIN_OFF => 6,
+      P_BASE     => P_BASE,
+      PWM_OFF    => 1,
+      PWM_W      => LUT_DAT_W)
     port map (
       ACK_O     => PWM_SL_ACK_O,
       CLK_I     => CLK_I,