library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tb_priority_encoder is
end tb_priority_encoder;

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architecture testbench of tb_priority_encoder is

  constant period : time := 1 us;
  constant offset : time := 0 us;

  signal CLK_I : std_logic;
  signal RST_I : std_logic;
  
  signal SEL  : std_logic_vector (3 downto 0);
  signal CODE : std_logic_vector (1 downto 0);

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begin
  
  uut: entity work.priority_encoder
    generic map (
      SEL_W  => 4,
      CODE_W => 2)
    port map (
      sel  => SEL,
      code => CODE);

  
  SYSCON_CLK : process is
  begin
    CLK_I <= '0';
    wait for offset;
    loop
      CLK_I <= '1';
      wait for period/2;
      CLK_I <= '0';
      wait for period/2;
    end loop;
  end process;

  SYSCON_RST : process is
  begin
    RST_I <= '0';
    wait for offset;
    wait for 0.75*period;
    RST_I <= '1';
    wait for 2*period;
    RST_I <= '0';
    wait;
  end process;

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  UUT_FEED : process is
  begin
    SEL <= "0000";
        
    wait for offset;
    wait for 3*period;

    for i in 1 to 15 loop
      SEL <= conv_std_logic_vector(i, 4);
      wait for 3*period;
    end loop;
    
    wait;
  end process;
  
end testbench;