library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity tb_multiplier is
end tb_multiplier;

--------------------------------------------------------------------------------

architecture testbench of tb_multiplier is

  constant period : time := 2 us;
  constant offset : time := 0 us;


  signal clk      : std_logic;
  signal reset    : std_logic;

  signal A     : std_logic_vector (15 downto 0);
  signal B     : std_logic_vector (15 downto 0);
  signal prod  : std_logic_vector (31 downto 0);

  signal test_vector_no : integer := 0;
  

  type test_vector_t is record
    A    : std_logic_vector (15 downto 0);
    B    : std_logic_vector (15 downto 0);
    prod : std_logic_vector (31 downto 0);
  end record;

  type test_vector_array is array (natural range<>) of test_vector_t;

  constant test_vectors : test_vector_array := (
    (X"0000", X"0000", X"00000000"),
    (X"0000", X"FFFF", X"00000000"),
    (X"0001", X"0001", X"00000001"),
    (X"7FFF", X"7FFF", X"3FFF0001"),
    (X"FFFF", X"0001", X"FFFFFFFF"),
    (X"FFFF", X"FFFF", X"00000001"),
    (X"8000", X"7FFF", X"C0008000"),
    (X"8000", X"FFFF", X"00008000"),
    (X"8001", X"8001", X"BFFEFFFF"),
    (X"8000", X"8000", X"C0000000"));
  
--------------------------------------------------------------------------------
  
begin

  uut : entity work.multiplier
    port map (
      A     => A,
      B     => B,
      prod  => prod);

  
  CLK_PROC : process
  begin
    clk <= '0';
    wait for offset;
    
    loop
      clk <= '1';
      wait for period/2;
      clk <= '0';
      wait for period/2;
    end loop;
  end process;


  RSET_PROC : process
  begin
    reset <= '0';
    wait for 1.5 * period;
    reset <= '1';
    wait for 1 * period;
    reset <= '0';
    wait;
  end process;


  TEST_VECTOR_PROC : process
  begin
    A <= (others => '0');
    B <= (others => '0');
    
    wait for offset;
    wait for 3 * period;
    
    for i in test_vectors'RANGE loop
      test_vector_no <= i;
      
      A <= test_vectors(i).A;      
      B <= test_vectors(i).B;
      wait for period;

      assert prod = test_vectors(i).prod
        report "Invalid product - test vector no. " & integer'image(i)
        severity warning;
    end loop;

    wait;
  end process;
  
end testbench;