library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tb_mcc_exec is end tb_mcc_exec; -------------------------------------------------------------------------------- architecture testbench of tb_mcc_exec is constant period : time := 500 ns; constant offset : time := 0 us; signal CLK_I : std_logic; signal RST_I : std_logic; signal MCC_AXIS_O : std_logic_vector (1 downto 0); signal MCC_DONE_O : std_logic; signal MCC_EXEC_I : std_logic; signal MCC_ERR_O : std_logic; signal MCC_ACK_I : std_logic; signal MCC_STB_O : std_logic; -------------------------------------------------------------------------------- begin uut : entity work.mcc_exec generic map ( AXIS_CNT => 3, AXIS_CNT_W => 2) port map ( CLK_I => CLK_I, RST_I => RST_I, MCC_AXIS_O => MCC_AXIS_O, MCC_DONE_O => MCC_DONE_O, MCC_EN_I => '1', MCC_EXEC_I => MCC_EXEC_I, MCC_ERR_O => MCC_ERR_O, MCC_ACK_I => MCC_ACK_I, MCC_STB_O => MCC_STB_O); MCC_EMULATION : process is begin MCC_ACK_I <= '0'; loop wait until MCC_STB_O = '1'; wait for 4*period; MCC_ACK_I <= '1'; wait until MCC_STB_O <= '0'; MCC_ACK_I <= '0'; end loop; end process MCC_EMULATION; SYSCON_CLK : process is begin CLK_I <= '0'; wait for offset; loop CLK_I <= '1'; wait for period/2; CLK_I <= '0'; wait for period/2; end loop; end process; SYSCON_RST : process is begin RST_I <= '0'; wait for offset; wait for 0.75*period; RST_I <= '1'; wait for 2*period; RST_I <= '0'; wait; end process; -------------------------------------------------------------------------------- UUT_FEED : process is begin MCC_EXEC_I <= '0'; wait for offset; wait for 4*period; for i in 0 to 1 loop wait for 0.25*period; MCC_EXEC_I <= '1'; wait for period; MCC_EXEC_I <= '0'; wait until MCC_DONE_O = '1'; wait for 8*period; end loop; wait; end process; end testbench;