2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
9 --------------------------------------------------------------------------------
11 architecture testbench of tb_mcc is
13 constant period : time := 500 ns;
14 constant offset : time := 0 us;
16 constant LUT_DAT_W : integer := 10;
17 constant LUT_ADR_W : integer := 9;
18 constant LUT_INIT_FILE : string := "../sin.lut";
19 constant IRF_ADR_W : integer := 5;
21 constant WAVE_SIZE : integer := 2**LUT_ADR_W;
24 signal ACK_O : std_logic;
25 signal CLK_I : std_logic;
26 signal RST_I : std_logic;
27 signal STB_I : std_logic;
29 signal IRF_ACK_I : std_logic;
30 signal IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
31 signal IRF_CYC_O : std_logic;
32 signal IRF_DAT_I : std_logic_vector (15 downto 0);
33 signal IRF_DAT_O : std_logic_vector (15 downto 0);
34 signal IRF_STB_O : std_logic;
35 signal IRF_WE_O : std_logic;
37 signal LUT_ADR_O : std_logic_vector (LUT_ADR_W-1 downto 0);
38 signal LUT_DAT_I : std_logic_vector (LUT_DAT_W-1 downto 0);
39 signal LUT_STB_O : std_logic;
42 subtype word_t is std_logic_vector (15 downto 0);
44 signal dbg_mem00 : word_t := "0000000000100100"; -- MCC enable flags (RO)
45 signal dbg_mem04 : word_t := (others => '0'); -- Angle (RO)
46 signal dbg_mem11 : word_t := (others => '0'); -- Phase 1
47 signal dbg_mem15 : word_t := (others => '0'); -- Phase 2
48 signal dbg_mem19 : word_t := (others => '0'); -- Phase 3
49 signal dbg_ack : std_logic := '0';
51 --------------------------------------------------------------------------------
57 LUT_ADR_W => LUT_ADR_W,
58 LUT_DAT_W => LUT_DAT_W,
59 IRF_ADR_W => IRF_ADR_W)
65 LUT_STB_O => LUT_STB_O,
66 LUT_ADR_O => LUT_ADR_O,
67 LUT_DAT_I => LUT_DAT_I,
68 IRC_DAT_I => (others => '0'),
73 IRF_ACK_I => IRF_ACK_I,
74 IRF_ADR_O => IRF_ADR_O,
75 IRF_DAT_I => IRF_DAT_I,
76 IRF_DAT_O => IRF_DAT_O,
77 IRF_STB_O => IRF_STB_O,
78 IRF_WE_O => IRF_WE_O);
80 wave_table_1 : entity work.wave_table
84 INIT_FILE => LUT_INIT_FILE)
89 DAT_I => (others => '0'),
95 SYSCON_CLK : process is
107 SYSCON_RST : process is
111 wait for 0.75*period;
119 DBG_MEM : process (IRF_STB_O, CLK_I) is
121 IRF_ACK_I <= IRF_STB_O and (IRF_WE_O or dbg_ack);
123 if rising_edge(CLK_I) then
124 dbg_ack <= IRF_STB_O;
127 if rising_edge(CLK_I) and IRF_STB_O = '1' then
128 if IRF_WE_O = '0' then
129 case conv_integer(IRF_ADR_O) is
130 when 16#00# => IRF_DAT_I <= dbg_mem00;
131 when 16#04# => IRF_DAT_I <= dbg_mem04;
132 when 16#11# => IRF_DAT_I <= dbg_mem11;
133 when 16#15# => IRF_DAT_I <= dbg_mem15;
134 when 16#19# => IRF_DAT_I <= dbg_mem19;
135 when others => IRF_DAT_I <= (others => '0');
138 case conv_integer(IRF_ADR_O) is
139 when 16#11# => dbg_mem11 <= IRF_DAT_O;
140 when 16#15# => dbg_mem15 <= IRF_DAT_O;
141 when 16#19# => dbg_mem19 <= IRF_DAT_O;
148 --------------------------------------------------------------------------------
150 UUT_FEED : process is
158 dbg_mem04 <= conv_std_logic_vector(i, 16);
161 wait until rising_edge(CLK_I) and ACK_O = '1';