1 //----------------------------------------------------------------------------
2 // Copyright (C) 2009 Authors
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28 //----------------------------------------------------------------------------
30 // *File Name: template_periph_8b.v
32 // *Module Description:
33 // 8 bit peripheral template.
36 // - Olivier Girard, olgirard@gmail.com
38 //----------------------------------------------------------------------------
40 // $LastChangedBy: olivier.girard $
41 // $LastChangedDate: 2010-03-07 09:09:38 +0100 (Sun, 07 Mar 2010) $
42 //----------------------------------------------------------------------------
43 `include "timescale.v"
44 `include "openMSP430_defines.v"
46 module template_periph_8b (
49 per_dout, // Peripheral data output
52 mclk, // Main system clock
53 per_addr, // Peripheral address
54 per_din, // Peripheral data input
55 per_en, // Peripheral enable (high active)
56 per_wen, // Peripheral write enable (high active)
57 puc // Main system reset
62 output [15:0] per_dout; // Peripheral data output
66 input mclk; // Main system clock
67 input [7:0] per_addr; // Peripheral address
68 input [15:0] per_din; // Peripheral data input
69 input per_en; // Peripheral enable (high active)
70 input [1:0] per_wen; // Peripheral write enable (high active)
71 input puc; // Main system reset
74 //=============================================================================
75 // 1) PARAMETER DECLARATION
76 //=============================================================================
79 parameter CNTRL1 = 9'h090;
80 parameter CNTRL2 = 9'h091;
81 parameter CNTRL3 = 9'h092;
82 parameter CNTRL4 = 9'h093;
85 // Register one-hot decoder
86 parameter CNTRL1_D = (256'h1 << (CNTRL1 /2));
87 parameter CNTRL2_D = (256'h1 << (CNTRL2 /2));
88 parameter CNTRL3_D = (256'h1 << (CNTRL3 /2));
89 parameter CNTRL4_D = (256'h1 << (CNTRL4 /2));
92 //============================================================================
93 // 2) REGISTER DECODER
94 //============================================================================
96 // Register address decode
100 (CNTRL1 /2): reg_dec = CNTRL1_D;
101 (CNTRL2 /2): reg_dec = CNTRL2_D;
102 (CNTRL3 /2): reg_dec = CNTRL3_D;
103 (CNTRL4 /2): reg_dec = CNTRL4_D;
104 default : reg_dec = {256{1'b0}};
108 wire reg_lo_write = per_wen[0] & per_en;
109 wire reg_hi_write = per_wen[1] & per_en;
110 wire reg_read = ~|per_wen & per_en;
112 // Read/Write vectors
113 wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
114 wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
115 wire [255:0] reg_rd = reg_dec & {256{reg_read}};
118 //============================================================================
120 //============================================================================
126 wire cntrl1_wr = CNTRL1[0] ? reg_hi_wr[CNTRL1/2] : reg_lo_wr[CNTRL1/2];
127 wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8] : per_din[7:0];
129 always @ (posedge mclk or posedge puc)
130 if (puc) cntrl1 <= 8'h00;
131 else if (cntrl1_wr) cntrl1 <= cntrl1_nxt;
138 wire cntrl2_wr = CNTRL2[0] ? reg_hi_wr[CNTRL2/2] : reg_lo_wr[CNTRL2/2];
139 wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8] : per_din[7:0];
141 always @ (posedge mclk or posedge puc)
142 if (puc) cntrl2 <= 8'h00;
143 else if (cntrl2_wr) cntrl2 <= cntrl2_nxt;
150 wire cntrl3_wr = CNTRL3[0] ? reg_hi_wr[CNTRL3/2] : reg_lo_wr[CNTRL3/2];
151 wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8] : per_din[7:0];
153 always @ (posedge mclk or posedge puc)
154 if (puc) cntrl3 <= 8'h00;
155 else if (cntrl3_wr) cntrl3 <= cntrl3_nxt;
162 wire cntrl4_wr = CNTRL4[0] ? reg_hi_wr[CNTRL4/2] : reg_lo_wr[CNTRL4/2];
163 wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8] : per_din[7:0];
165 always @ (posedge mclk or posedge puc)
166 if (puc) cntrl4 <= 8'h00;
167 else if (cntrl4_wr) cntrl4 <= cntrl4_nxt;
171 //============================================================================
172 // 4) DATA OUTPUT GENERATION
173 //============================================================================
176 wire [15:0] cntrl1_rd = (cntrl1 & {8{reg_rd[CNTRL1/2]}}) << (8 & {4{CNTRL1[0]}});
177 wire [15:0] cntrl2_rd = (cntrl2 & {8{reg_rd[CNTRL2/2]}}) << (8 & {4{CNTRL2[0]}});
178 wire [15:0] cntrl3_rd = (cntrl3 & {8{reg_rd[CNTRL3/2]}}) << (8 & {4{CNTRL3[0]}});
179 wire [15:0] cntrl4_rd = (cntrl4 & {8{reg_rd[CNTRL4/2]}}) << (8 & {4{CNTRL4[0]}});
181 wire [15:0] per_dout = cntrl1_rd |
187 endmodule // template_periph_8b
189 `include "openMSP430_undefines.v"