Implement ITT conditional execution

[fpga/lx-cpu1/tumbl.git] / hw / core_ctrl.vhd

diff --git a/hw/core_ctrl.vhd b/hw/core_ctrl.vhd
index a0d714332eff8bf4fbf98c21c7cd80f9c85dc76e..55c5344d40f7169718d41d179b62043e81d1d8e2 100644 (file)
--- a/hw/core_ctrl.vhd
+++ b/hw/core_ctrl.vhd
@@ -51,6 +51,7 @@ ENTITY core_ctrl IS
         -- exeq to fetch feedback registers
         EX2IF_REG_i     :  IN EX2IF_Type;
         EX2IF_REG_o     : OUT EX2IF_Type;
+        EX2CTRL_REG_i   :  IN EX2CTRL_Type;
         -- exeq to core (halting)
         exeq_halt_i     :  IN STD_LOGIC;
         -- exeq to mem pipeline registers
@@ -85,12 +86,13 @@ ARCHITECTURE rtl OF core_ctrl IS
 
     SIGNAL rst_r          : STD_LOGIC;
     SIGNAL reset_s        : STD_LOGIC;
-    SIGNAL core_clken_s  : STD_LOGIC;
+    SIGNAL core_clken_s   : STD_LOGIC;
 
     SIGNAL ID2EX_REG_r    : ID2EX_Type;
     SIGNAL EX2IF_REG_r    : EX2IF_Type;
     SIGNAL IMM_LOCK_r     : IMM_LOCK_Type;
     SIGNAL HAZARD_WRB_r   : HAZARD_WRB_Type;
+    SIGNAL flush_second_r : STD_LOGIC;
     SIGNAL delayBit_r     : STD_LOGIC;
     SIGNAL clken_s        : STD_LOGIC;
     SIGNAL clken_pipe_s   : STD_LOGIC;
@@ -118,7 +120,7 @@ BEGIN
     gprf_clken_o   <= clken_s;
     -- signals for clearing the ID2EX and EX2MEM registers during branches
     flush_ID2EX_s  <= ((EX2IF_REG_i.take_branch AND (NOT delayBit_r)) OR EX2IF_REG_r.take_branch) WHEN COMPATIBILITY_MODE_g = TRUE
-                      ELSE (EX2IF_REG_i.take_branch OR EX2IF_REG_r.take_branch);
+                      ELSE (EX2IF_REG_i.take_branch OR EX2IF_REG_r.take_branch OR EX2CTRL_REG_i.flush_first OR flush_second_r);
     flush_EX2MEM_s <= HAZARD_WRB_i.hazard;
     -- outputs that need to be readable too, so needing shadowing signals
     ID2EX_REG_o    <= ID2EX_REG_r;
@@ -137,7 +139,7 @@ regd_proc:
               flush_ID2EX_s, flush_EX2MEM_s, HAZARD_WRB_i,
               MEM_REG_i, ID2CTRL_i, int_i, MSR_i,
               int_busy_r, IMM_LOCK_i, ID2EX_REG_i, ID2EX_REG_r,
-              EX2IF_REG_i, EX_WRB_i, EX2MEM_REG_i )
+              EX2IF_REG_i, EX2CTRL_REG_i, EX_WRB_i, EX2MEM_REG_i )
 
         -- some local procedures
         PROCEDURE lp_rst_IF2ID_REG IS
@@ -229,7 +231,9 @@ regd_proc:
                 lp_rst_MEM_REG;
 
                 IF (COMPATIBILITY_MODE_g = TRUE) THEN
-                    delayBit_r    <= '0';
+                    delayBit_r     <= '0';
+                ELSE
+                    flush_second_r <= '0';
                 END IF;
 
                 flush_ID2EX_r <= '0';
@@ -241,6 +245,9 @@ regd_proc:
                     IF2ID_REG_o <= IF2ID_REG_i;
                 END IF;
                 flush_ID2EX_r <= flush_ID2EX_s;
+                IF (COMPATIBILITY_MODE_g = FALSE) THEN
+                    flush_second_r <= EX2CTRL_REG_i.flush_second;
+                END IF;
                 HAZARD_WRB_r  <= HAZARD_WRB_i;
                 MEM_REG_o     <= MEM_REG_i;
                 int_busy_r    <= ID2CTRL_i.int_busy;
@@ -279,8 +286,8 @@ regd_proc:
                 lp_rst_IMM_LOCK;
             ELSE
                 IF (clken_pipe_s = '1') THEN
-                    EX2IF_REG_r <= EX2IF_REG_i;
-                    EX_WRB_o    <= EX_WRB_i;
+                    EX2IF_REG_r   <= EX2IF_REG_i;
+                    EX_WRB_o      <= EX_WRB_i;
                 END IF;
                 IF (clken_s = '1') THEN
                     -- next test to prevent a flush from disrupting