Add back support for delay slot, but with writing PC+4 when linking and using delay...

[fpga/lx-cpu1/tumbl.git] / hw / core_ctrl.vhd

diff --git a/hw/core_ctrl.vhd b/hw/core_ctrl.vhd
index 991a1c2aa27dab380b24a8ac2ff0f0c3ccfc72a7..897a9411607f83118c500993db3b27ca42512e9f 100644 (file)
--- a/hw/core_ctrl.vhd
+++ b/hw/core_ctrl.vhd
@@ -34,7 +34,6 @@ ENTITY core_ctrl IS
                clk_i           :  IN STD_LOGIC;
                rst_i           :  IN STD_LOGIC;
                halt_i          :  IN STD_LOGIC;
-               bad_op_i        :  IN STD_LOGIC;
                int_i           :  IN STD_LOGIC;
                trace_i         :  IN STD_LOGIC;
                trace_kick_i    :  IN STD_LOGIC;
@@ -49,6 +48,7 @@ ENTITY core_ctrl IS
                -- decode to exeq pipeline registers
                ID2EX_REG_i     :  IN ID2EX_Type;
                ID2EX_REG_o     : OUT ID2EX_Type;
+               delay_bit_o     : OUT STD_LOGIC;
                -- GPRF control
                gprf_clken_o    : OUT STD_LOGIC;
                -- exeq to fetch feedback registers
@@ -117,7 +117,7 @@ BEGIN
        imem_addr_o    <= IF2ID_REG_i.program_counter;
        -- Tracing
        -- Reset_s is 1 when rst_i is one and then gets deactivated
-       core_clken_s  <= reset_s OR ((NOT bad_op_i) AND (((NOT trace_i) AND (NOT exeq_halt_i)) OR trace_kick_i));
+       core_clken_s  <= reset_s OR (((NOT trace_i) AND (NOT exeq_halt_i)) OR trace_kick_i);
        core_clken_o  <= core_clken_s;
        -- clock/wait control lines
        clken_s        <= MEM2CTRL_i.clken OR rst_i;
@@ -126,11 +126,12 @@ BEGIN
        gprf_clken_o   <= clken_s;
        -- signals for clearing the ID2EX and EX2MEM registers during branches
        flush_ID2EX_s  <= ((EX2IF_REG_i.take_branch AND (NOT delayBit_r)) OR EX2IF_REG_r.take_branch) WHEN COMPATIBILITY_MODE_g = TRUE
-                                                                               ELSE (EX2IF_REG_i.take_branch OR EX2IF_REG_r.take_branch OR EX2CTRL_REG_i.flush_first OR flush_first_r OR
-                                                                                               ((NOT EX2CTRL_REG_i.ignore_state) AND (NOT ignore_state_r) AND flush_second_2r));
+                                                                               ELSE ((EX2IF_REG_i.take_branch AND (NOT delayBit_r)) OR EX2IF_REG_r.take_branch OR EX2CTRL_REG_i.flush_first OR
+                                                                                               flush_first_r OR ((NOT EX2CTRL_REG_i.ignore_state) AND (NOT ignore_state_r) AND flush_second_2r));
        flush_EX2MEM_s <= HAZARD_WRB_i.hazard;
        -- outputs that need to be readable too, so needing shadowing signals
        ID2EX_REG_o    <= ID2EX_REG_r;
+       delay_bit_o    <= delayBit_r;
        EX2IF_REG_o    <= EX2IF_REG_r;
        IMM_LOCK_o     <= IMM_LOCK_r;
        HAZARD_WRB_o   <= HAZARD_WRB_r;
@@ -242,10 +243,9 @@ regd_proc:
                        lp_rst_MSR;
                        lp_rst_HAZARD_WRB;
                        lp_rst_MEM_REG;
+                       delayBit_r        <= '0';
 
-                       IF (COMPATIBILITY_MODE_g = TRUE) THEN
-                               delayBit_r      <= '0';
-                       ELSE
+                       IF (COMPATIBILITY_MODE_g = FALSE) THEN
                                flush_first_r   <= '0';
                                flush_second_r  <= '0';
                                flush_second_2r <= '0';
@@ -286,9 +286,7 @@ regd_proc:
                IF ((reset_s = '1') OR (flush_ID2EX_s = '1')) THEN
                        setup_int_r <= '0';
                        lp_rst_ID2EX_REG;
-                       IF (COMPATIBILITY_MODE_g = TRUE) THEN
-                               delayBit_r <= '0';
-                       END IF;
+                       delayBit_r <= '0';
                -- check for the need and possibility to handle active interrupt requests
                ELSIF (((int_i = '1') OR (MEM2CTRL_i.int = '1')) AND (MSR_i.IE = '1') AND
                                        (ID2CTRL_i.int_busy = '0') AND (int_busy_r = '0') AND
@@ -305,9 +303,7 @@ regd_proc:
                ELSIF (clken_pipe_s = '1') THEN
                        setup_int_r <= '0';
                        ID2EX_REG_r <= ID2EX_REG_i;
-                       IF (COMPATIBILITY_MODE_g = TRUE) THEN
-                               delayBit_r  <= ID2CTRL_i.delayBit;
-                       END IF;
+                       delayBit_r  <= ID2CTRL_i.delayBit;
                END IF;
                -- exeq-to-mem unit registers
                IF ((reset_s = '1') OR (flush_EX2MEM_s = '1')) THEN