Attempt to fix forward from memory read to write over when Tumbl is being to stop.

[fpga/lx-cpu1/tumbl.git] / hw / mem.vhd

diff --git a/hw/mem.vhd b/hw/mem.vhd
index 139451c0385c04837133479a957b475754eed535..18417293711bfec7abaf1c8a9b9c5f886e60f9ed 100644 (file)
--- a/hw/mem.vhd
+++ b/hw/mem.vhd
@@ -16,7 +16,7 @@
 
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.all;
-USE work.mbl_Pkg.all;
+USE WORK.mbl_pkg.all;
 
 --------------------------------------------------------------------------------
 ENTITY mem IS
@@ -54,10 +54,9 @@ BEGIN
        MEM_WRB_o.wrb_Action <= MEM_REG_i.wrb_Action;
        MEM_WRB_o.wrix_rD    <= MEM_REG_i.wrix_rD;
        -- also signal 'slow memory decices' and interrupts from devices
-       MEM2CTRL_o.clken <= DMEMB_i.clken;
+       MEM2CTRL_o.bus_taken <= '0' WHEN EX2MEM_i.mem_Action = NO_MEM ELSE DMEMB_i.bus_taken;
+       MEM2CTRL_o.bus_wait  <= '0' WHEN EX2MEM_i.mem_Action = NO_MEM ELSE DMEMB_i.bus_wait;
        MEM2CTRL_o.int   <= DMEMB_i.int;
-       -- pass byte_select signal (NOTE: BIG ENDIAN)
-       DMEMB_o.bSel     <= EX2MEM_i.byte_Enable;
 
 p_mem:
        PROCESS (EX2MEM_i, DMEMB_i, MEM_REG_i)
@@ -77,14 +76,17 @@ p_mem:
                        WHEN OTHERS => dmem_data_v :=              DMEMB_i.data;
                END CASE;
 
+               MEM2CTRL_o.read_data <= dmem_data_v;
+               MEM2CTRL_o.need_keep <= '0';
+
                -- output to dmem-bus
                CASE EX2MEM_i.mem_Action IS
 
                        WHEN WR_MEM =>
                                -- write (or forward) to data memory bus
-                               DMEMB_o.addr <= EX2MEM_i.exeq_result;
-                               DMEMB_o.ena  <= '1';
-                               DMEMB_o.wre  <= '1';
+                               DMEMB_o.addr  <= EX2MEM_i.exeq_result(16 downto 2);
+                               DMEMB_o.rd    <= '0';
+                               DMEMB_o.bls   <= EX2MEM_i.byte_Enable;
                                -- Note: use MEM_REG_i here, since MEM_WRB_o (output) cannot be read
                                IF ((MEM_REG_i.wrb_Action /= NO_WRB) AND
                                        (EX2MEM_i.wrix_rD = MEM_REG_i.wrix_rD)) THEN
@@ -95,6 +97,7 @@ p_mem:
                                                WHEN OTHERS  =>
                                                        -- forward mem_data just read, to handle e.g. lhu rD,mem[x]; sh rD,mem[y]; ...
                                                        exeq_data_v := dmem_data_v;
+                                                       MEM2CTRL_o.need_keep <= '1';
                                        END CASE;
                                ELSE
                                        exeq_data_v := EX2MEM_i.data_rD;
@@ -112,15 +115,15 @@ p_mem:
 
                        WHEN RD_MEM =>
                                -- read from data memory bus
-                               DMEMB_o.addr <= EX2MEM_i.exeq_result;
-                               DMEMB_o.ena  <= '1';
-                               DMEMB_o.wre  <= '0';
+                               DMEMB_o.addr <= EX2MEM_i.exeq_result(16 downto 2);
+                               DMEMB_o.rd   <= '1';
+                               DMEMB_o.bls  <= (others => '0');
                                DMEMB_o.data <= EX2MEM_i.data_rD;   -- (OTHERS => 'Z');
 
                        WHEN OTHERS =>      -- NO_MEM
-                               DMEMB_o.addr <= C_32_ZEROS;
-                               DMEMB_o.ena  <= '0';
-                               DMEMB_o.wre  <= '0';
+                               DMEMB_o.addr <= (others => '0');
+                               DMEMB_o.rd   <= '0';
+                               DMEMB_o.bls  <= (others => '0');
                                DMEMB_o.data <= EX2MEM_i.data_rD;   -- (OTHERS => 'Z');
                END CASE;