From dcdda297369b38c6a5b9c0fb5094cb5f219b1f32 Mon Sep 17 00:00:00 2001
From: Martin Meloun <meloumar@cmp.felk.cvut.cz>
Date: Mon, 26 Aug 2013 12:46:59 +0200
Subject: [PATCH] Implement reset properly with correct polarity inside the
 modules

---
 hw/bcd.vhd          | 12 +++++-------
 hw/irc_register.vhd |  2 +-
 hw/lx_rocon_top.vhd |  5 ++---
 hw/qcounter.vhd     | 42 ++++++++++++++++++++++++------------------
 4 files changed, 32 insertions(+), 29 deletions(-)

diff --git a/hw/bcd.vhd b/hw/bcd.vhd
index 0e2954f..671d12b 100644
--- a/hw/bcd.vhd
+++ b/hw/bcd.vhd
@@ -33,17 +33,15 @@ begin
 
 	value <= counter;
 
-	update: process (clk)
+	update: process (clk, reset)
 	begin
 
-		if clk = '1' and clk'event then
-
-			if reset = '0' then
-				counter <= (others => '0');
-			elsif en = '0' then
+		if reset = '1' then
+			counter <= (others => '0');
+		elsif clk = '1' and clk'event then
+			if en = '0' then
 				counter <= counter + 1;
 			end if;
-
 		end if;
 
 	end process;
diff --git a/hw/irc_register.vhd b/hw/irc_register.vhd
index 7847619..2c76c2c 100644
--- a/hw/irc_register.vhd
+++ b/hw/irc_register.vhd
@@ -78,7 +78,7 @@ begin
 	begin
 		if clk = '1' and clk'event then
 
-			if reset = '0' then
+			if reset = '1' then
 
 				qcount_error <= '0';
 				qcount_index <= (others => '0');
diff --git a/hw/lx_rocon_top.vhd b/hw/lx_rocon_top.vhd
index 3b7b33b..538b33d 100644
--- a/hw/lx_rocon_top.vhd
+++ b/hw/lx_rocon_top.vhd
@@ -390,8 +390,7 @@ begin
 	end process;
 
 	-- If RD and BLS is not high, we must keep DATA at high impedance
-	-- or the FPGA collides with SDRAM (burning each other)
-
+	-- or the FPGA collides with SDRAM (damaging each other)
 	memory_bus_out: process(cs0_xc, rd, data, data_read)
 	begin
 
@@ -411,7 +410,7 @@ begin
 	initialization: process(init)
 	begin
 
-		reset <= init;
+		reset <= not init;
 
 	end process;
 
diff --git a/hw/qcounter.vhd b/hw/qcounter.vhd
index 8df047f..8bbb913 100644
--- a/hw/qcounter.vhd
+++ b/hw/qcounter.vhd
@@ -57,7 +57,7 @@ begin
 	qcount(1) <= b;
 	qcount(31 downto 2) <= count;
 
-  comb_event: process (a_prev, b_prev, a, b)
+  comb_event: process (reset, a_prev, b_prev, a, b)
   begin
     a_rise <= '0';
     a_fall <= '0';
@@ -65,21 +65,26 @@ begin
     b_fall <= '0';
     ab_event <= '0';
     ab_error <= '0';
-    if ((a xor a_prev) and (b xor b_prev)) = '1' then
-      -- forbidden double transition
-      ab_error <= '1';
-    else
-      a_rise <= (a xor a_prev) and a;
-      a_fall <= (a xor a_prev) and not a;
-      b_rise <= (b xor b_prev) and b;
-      b_fall <= (b xor b_prev) and not b;
-      ab_event <= (a xor a_prev) or (b xor b_prev);
-    end if;
+
+		if reset = '0' then
+			if ((a xor a_prev) and (b xor b_prev)) = '1' then
+				-- forbidden double transition
+				ab_error <= '1';
+			else
+				a_rise <= (a xor a_prev) and a;
+				a_fall <= (a xor a_prev) and not a;
+				b_rise <= (b xor b_prev) and b;
+				b_fall <= (b xor b_prev) and not b;
+				ab_event <= (a xor a_prev) or (b xor b_prev);
+			end if;
+		end if;
   end process;
 
-  comb_count: process (a_prev, b_prev, a, b, count, count_prev)
+  comb_count: process (reset, a_prev, b_prev, a, b, count, count_prev)
   begin
-    if (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
+		if reset = '1' then
+			count <= count_prev;
+		elsif (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
       count <= count_prev + 1;
     elsif (a_prev = '0') and (b_prev = '0') and (a = '0') and (b = '1') then
       count <= count_prev - 1;
@@ -88,15 +93,16 @@ begin
     end if;
   end process;
 
-  seq: process (clk)
+  seq: process (clk, reset, a, b)
   begin
-    if clk = '1' and clk'event then
+    if reset = '1' then
+			count_prev <= (others => '0');
+		end if;
+
+		if clk = '1' and clk'event then
 			if reset = '0' then
-				count_prev <= (others => '0');
-			else
 				count_prev <= count;
 			end if;
-
 			a_prev <= a;
 			b_prev <= b;
 		end if;
-- 
2.39.2