From 8c5253507c9e2cd24f2d831963477db91b782148 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sun, 7 Dec 2014 22:46:57 +0100 Subject: [PATCH] Tumbl firmware which tracks IRC0 and computes sine and cosine with use of approximation block. Signed-off-by: Pavel Pisa --- hw/Makefile | 9 ++- hw/lx-rocon_firmware/firmware.c | 97 +++++++++++++++++++++++++++++++ hw/lx-rocon_firmware/tumbl_addr.h | 85 +++++++++++++++++++++++++++ 3 files changed, 190 insertions(+), 1 deletion(-) create mode 100644 hw/lx-rocon_firmware/firmware.c create mode 100644 hw/lx-rocon_firmware/tumbl_addr.h diff --git a/hw/Makefile b/hw/Makefile index f67a1c0..dbfd278 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -220,10 +220,17 @@ $(OUT)/bin2mem: $(FIRMWARE_DIR)/utils/bin2mem.c re-firmware $(REQ_FIRMWARE): $(REQ_PKG) $(OUT)/bin2mem $(OUT)/firmware.elf $(TARGET_OBJCOPY) -O binary $(OUT)/firmware.elf -j .text -S $(OUT)/imem.bin $(TARGET_OBJCOPY) -O binary $(OUT)/firmware.elf -j .data -S $(OUT)/dmem.bin - $(TARGET_OBJDUMP) -DSCz $(OUT)/firmware.elf > $@ + $(TARGET_OBJDUMP) -DSCz $(OUT)/firmware.elf >$(OUT)/firmware.lst cd $(OUT); \ $(TARGET_OBJDUMP) -b binary -mmbtumbl -EB -D imem.bin | sed -e 's/.data/.text/' > imem.asm +# imem +# watch -d ./usb_sendhex -d 0x1669:0x1023 -t 4 -s 0x80000000 -l 0x200 -f dump -u - +# dmem +# watch -d ./usb_sendhex -d 0x1669:0x1023 -t 4 -s 0x80001000 -l 0x200 -f dump -u - +# PC +# watch -d ./usb_sendhex -d 0x1669:0x1023 -t 4 -s 0x80003008 -l 0x4 -f dump -u - + #=============================================================================== .PHONY: clean diff --git a/hw/lx-rocon_firmware/firmware.c b/hw/lx-rocon_firmware/firmware.c new file mode 100644 index 0000000..d08cb56 --- /dev/null +++ b/hw/lx-rocon_firmware/firmware.c @@ -0,0 +1,97 @@ +/* Firmware file for lx-rocon tumbl coprocessor */ + +#include +#include "tumbl_addr.h" + +typedef struct pxmcc_axis_data_t { + uint32_t ptirc; /* IRC count per phase table */ + uint32_t ptper; /* number of periods per table */ + uint32_t ptreci; /* number of periods per table */ + uint32_t ptofs; /* offset between table and IRC counter */ + int32_t ptsin; + int32_t ptcos; +} pxmcc_axis_data_t; + +uint32_t sin_lat[7]; + +pxmcc_axis_data_t pxmcc_axis[1]; + +void init_defvals(void) +{ +} + +void find_sin_lat(void) +{ + int i; + register uint32_t a0, a1, a2, a3, a4, a5; + + *FPGA_FNCAPPROX_SIN = 0; + + for (i = 0; i < 20; i++) + asm volatile("": : : "memory"); + + *FPGA_FNCAPPROX_SIN = 0x40000000; + a0 = *FPGA_FNCAPPROX_SIN; + a1 = *FPGA_FNCAPPROX_SIN; + a2 = *FPGA_FNCAPPROX_SIN; + a3 = *FPGA_FNCAPPROX_SIN; + a4 = *FPGA_FNCAPPROX_SIN; + a5 = *FPGA_FNCAPPROX_SIN; + asm volatile("": : : "memory"); + + sin_lat[0] = 0x1234; + sin_lat[1] = a1; + sin_lat[2] = a2; + sin_lat[3] = a3; + sin_lat[4] = a4; + sin_lat[5] = a5; + sin_lat[6] = 0x4321; +} + +void main(void) +{ + pxmcc_axis_data_t *pxmcc = pxmcc_axis; + + pxmcc->ptirc = *FPGA_IRC0; + pxmcc->ptofs = pxmcc->ptirc; + pxmcc->ptper = 2000; + pxmcc->ptreci = 2147484; /* (1LL<<32)/ptper */ + + asm volatile("": : : "memory"); + + find_sin_lat(); + + while (1) { + uint32_t irc = *FPGA_IRC0; + uint32_t ofs = pxmcc->ptofs; + uint32_t per = pxmcc->ptper; + int32_t pti; + uint32_t pta; + uint32_t dummy; + + pti = irc - ofs; + if ((uint32_t)pti >= per) { + if (pti < 0) { + ofs -= per; + } else { + ofs += per; + } + pti = irc - ofs; + pxmcc->ptofs = ofs; + } + pxmcc->ptirc = pti; + + pta = pti * pxmcc->ptreci; + + *FPGA_FNCAPPROX_SIN = pta; + + dummy = *FPGA_FNCAPPROX_SIN; + dummy = *FPGA_FNCAPPROX_SIN; + dummy = *FPGA_FNCAPPROX_SIN; + pxmcc->ptsin = *FPGA_FNCAPPROX_SIN; + dummy = *FPGA_FNCAPPROX_COS; + pxmcc->ptcos = *FPGA_FNCAPPROX_COS; + + asm volatile("": : : "memory"); + } +} diff --git a/hw/lx-rocon_firmware/tumbl_addr.h b/hw/lx-rocon_firmware/tumbl_addr.h new file mode 100644 index 0000000..53a9093 --- /dev/null +++ b/hw/lx-rocon_firmware/tumbl_addr.h @@ -0,0 +1,85 @@ +#ifndef _TUMBL_ADDR_H +#define _TUMBL_ADDR_H + +#include + +#ifndef IOPORT32BIT + #define IO32ADDR(_val) ((volatile uint32_t *)(_val)) +#endif /*IOPORT32BIT*/ + +#define FPGA_IRC_BASE 0x00002000 + +#define FPGA_IRC0 IO32ADDR(FPGA_IRC_BASE+0x0000) +#define FPGA_IRC1 IO32ADDR(FPGA_IRC_BASE+0x0008) +#define FPGA_IRC2 IO32ADDR(FPGA_IRC_BASE+0x0010) +#define FPGA_IRC3 IO32ADDR(FPGA_IRC_BASE+0x0018) +#define FPGA_IRC4 IO32ADDR(FPGA_IRC_BASE+0x0020) +#define FPGA_IRC5 IO32ADDR(FPGA_IRC_BASE+0x0028) +#define FPGA_IRC6 IO32ADDR(FPGA_IRC_BASE+0x0030) +#define FPGA_IRC7 IO32ADDR(FPGA_IRC_BASE+0x0038) + +#define FPGA_FNCAPPROX_BASE 0x00003000 + +#define FPGA_FNCAPPROX IO32ADDR(FPGA_FNCAPPROX_BASE) +#define FPGA_FNCAPPROX_RECI IO32ADDR(FPGA_FNCAPPROX_BASE+0x04) +#define FPGA_FNCAPPROX_SIN IO32ADDR(FPGA_FNCAPPROX_BASE+0x08) +#define FPGA_FNCAPPROX_COS IO32ADDR(FPGA_FNCAPPROX_BASE+0x0c) + +#define FPGA_LX_MASTER_BASE 0x00004000 + +#define FPGA_LX_MASTER_TX IO32ADDR(FPGA_LX_MASTER_BASE+0x0000) + +/* pwm_reg += LX_MASTER_DATA_OFFS + 1 + (chan >> 3) + chan; */ + +#define FPGA_LX_MASTER_TX_PWM0 (FPGA_LX_MASTER_TX+9) +#define FPGA_LX_MASTER_TX_PWM1 (FPGA_LX_MASTER_TX+10) +#define FPGA_LX_MASTER_TX_PWM2 (FPGA_LX_MASTER_TX+11) +#define FPGA_LX_MASTER_TX_PWM3 (FPGA_LX_MASTER_TX+12) +#define FPGA_LX_MASTER_TX_PWM4 (FPGA_LX_MASTER_TX+13) +#define FPGA_LX_MASTER_TX_PWM5 (FPGA_LX_MASTER_TX+14) +#define FPGA_LX_MASTER_TX_PWM6 (FPGA_LX_MASTER_TX+15) +#define FPGA_LX_MASTER_TX_PWM7 (FPGA_LX_MASTER_TX+16) + +#define FPGA_LX_MASTER_TX_PWM8 (FPGA_LX_MASTER_TX+18) +#define FPGA_LX_MASTER_TX_PWM9 (FPGA_LX_MASTER_TX+19) +#define FPGA_LX_MASTER_TX_PWM10 (FPGA_LX_MASTER_TX+20) +#define FPGA_LX_MASTER_TX_PWM11 (FPGA_LX_MASTER_TX+21) +#define FPGA_LX_MASTER_TX_PWM12 (FPGA_LX_MASTER_TX+22) +#define FPGA_LX_MASTER_TX_PWM13 (FPGA_LX_MASTER_TX+23) +#define FPGA_LX_MASTER_TX_PWM14 (FPGA_LX_MASTER_TX+24) +#define FPGA_LX_MASTER_TX_PWM15 (FPGA_LX_MASTER_TX+25) + +#define FPGA_LX_MASTER_RX IO32ADDR(FPGA_LX_MASTER_BASE+0x0400) + +/* rec_reg += LX_MASTER_DATA_OFFS + 1 + (chan >> 3) * 3 + chan * 2; */ + +#define FPGA_LX_MASTER_RX_ADC0 (FPGA_LX_MASTER_RX+9) +#define FPGA_LX_MASTER_RX_ADC1 (FPGA_LX_MASTER_RX+11) +#define FPGA_LX_MASTER_RX_ADC2 (FPGA_LX_MASTER_RX+13) +#define FPGA_LX_MASTER_RX_ADC3 (FPGA_LX_MASTER_RX+15) +#define FPGA_LX_MASTER_RX_ADC4 (FPGA_LX_MASTER_RX+17) +#define FPGA_LX_MASTER_RX_ADC5 (FPGA_LX_MASTER_RX+19) +#define FPGA_LX_MASTER_RX_ADC6 (FPGA_LX_MASTER_RX+21) +#define FPGA_LX_MASTER_RX_ADC7 (FPGA_LX_MASTER_RX+23) + +#define FPGA_LX_MASTER_RX_VIN (FPGA_LX_MASTER_RX+25) + +#define FPGA_LX_MASTER_RX_ADC8 (FPGA_LX_MASTER_RX+28) +#define FPGA_LX_MASTER_RX_ADC9 (FPGA_LX_MASTER_RX+30) +#define FPGA_LX_MASTER_RX_ADC10 (FPGA_LX_MASTER_RX+32) +#define FPGA_LX_MASTER_RX_ADC11 (FPGA_LX_MASTER_RX+34) +#define FPGA_LX_MASTER_RX_ADC12 (FPGA_LX_MASTER_RX+36) +#define FPGA_LX_MASTER_RX_ADC13 (FPGA_LX_MASTER_RX+38) +#define FPGA_LX_MASTER_RX_ADC14 (FPGA_LX_MASTER_RX+40) +#define FPGA_LX_MASTER_RX_ADC15 (FPGA_LX_MASTER_RX+42) + +#define FPGA_LX_MASTER_CTRL IO32ADDR(FPGA_LX_MASTER_BASE+0x1000) + +#define FPGA_LX_MASTER_RESET (FPGA_LX_MASTER_CTRL+0) +#define FPGA_LX_MASTER_TX_REG (FPGA_LX_MASTER_CTRL+1) +#define FPGA_LX_MASTER_TX_WDOG (FPGA_LX_MASTER_CTRL+2) +#define FPGA_LX_MASTER_TX_CYCLE (FPGA_LX_MASTER_CTRL+3) +#define FPGA_LX_MASTER_RX_REG (FPGA_LX_MASTER_CTRL+4) +#define FPGA_LX_MASTER_RX_DDIV (FPGA_LX_MASTER_CTRL+5) + +#endif /* _TUMBL_ADDR_H */ -- 2.39.2