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(parent: 1cbc7ca) | patch
Correct FPGA bus design for external CPU read cycle.
authorPavel Pisa <ppisa@pikron.com>
Sun, 15 Feb 2015 18:08:40 +0000 (19:08 +0100)
committerPavel Pisa <ppisa@pikron.com>
Sun, 15 Feb 2015 18:08:40 +0000 (19:08 +0100)
commite4a407ddd154d1ef0fa3dcb8ce17f26bd9a363e2
tree2877bea5d4d0b4093189eedf07d4d6b67cc0d350tree | snapshot
parent1cbc7ca204f35cd40ac665814e7715e6ea3fa595commit | diff
Correct FPGA bus design for external CPU read cycle.

The original design required to keep peripheral
chip/clock enable signal for two clock cycles
during read to ensure correct output data routing.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
hw/bus_tumbl.vhd diff | blob | history
hw/lx_rocon_top.vhd diff | blob | history
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