library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.lx_rocon_pkg.all;

-- D circuit (filtered)

entity dff2 is
  port
	(
    clk_i   : in std_logic;
		reset_i : in std_logic;
    d_i     : in std_logic;
    q_o     : out std_logic
  );
end dff2;

architecture behavioral of dff2 is
	signal last_d_s : std_logic;
  signal data_s : std_logic;
begin
  q_o <= data_s;

seq:
	process
	begin
    wait until clk_i'event and clk_i = '1';
		if reset_i = '1' then
			last_d_s <= '0';
			data_s <= '0';
		else
			if d_i = last_d_s then
				data_s <= d_i;
			end if;
		end if;

		last_d_s <= d_i;
  end process;

end behavioral;