library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.mbl_pkg.all; use work.lx_rocon_pkg.all; -- IRC bus interconnect entity bus_irc is port ( clk_i : in std_logic; reset_i : in std_logic; -- Data bus address_i : in std_logic_vector(4 downto 0); next_ce_i : in std_logic; data_i : in std_logic_vector(31 downto 0); data_o : out std_logic_vector(31 downto 0); -- bls_i : in std_logic_vector(3 downto 0); -- Signals for IRC irc_i : in IRC_INPUT_Array_Type(7 downto 0) ); end bus_irc; architecture Behavioral of bus_irc is signal irc_o_s : IRC_OUTPUT_Array_Type(7 downto 0); signal reset_index_event_s : std_logic_vector(7 downto 0); signal reset_index_event2_s : std_logic_vector(7 downto 0); signal reset_ab_error_s : std_logic_vector(7 downto 0); signal state_o_s : std_logic_vector(3 downto 0); signal state_o_r : std_logic_vector(3 downto 0); -- signal irc_en_s : std_logic; signal irc_bls_s : std_logic_vector(3 downto 0); signal irc_addr_s : std_logic_vector(3 downto 0); signal irc_data_s : std_logic_vector(31 downto 0); signal irc_out_s : std_logic; signal irc_out_r : std_logic; -- signal reset_reg_s : std_logic; signal reset_reg_r : std_logic; signal reset_reg_wr_s : std_logic; -- signal reset_s : std_logic; signal ce_s : std_logic; begin irc0 : irc_reader port map ( clk_i => clk_i, reset_i => reset_s, irc_i => irc_i(0), reset_index_event_i => reset_index_event_s(0), reset_index_event2_i => reset_index_event2_s(0), reset_ab_error_i => reset_ab_error_s(0), irc_o => irc_o_s(0) ); irc1 : irc_reader port map ( clk_i => clk_i, reset_i => reset_s, irc_i => irc_i(1), reset_index_event_i => reset_index_event_s(1), reset_index_event2_i => reset_index_event2_s(1), reset_ab_error_i => reset_ab_error_s(1), irc_o => irc_o_s(1) ); irc2 : irc_reader port map ( clk_i => clk_i, reset_i => reset_s, irc_i => irc_i(2), reset_index_event_i => reset_index_event_s(2), reset_index_event2_i => reset_index_event2_s(2), reset_ab_error_i => reset_ab_error_s(2), irc_o => irc_o_s(2) ); irc3 : irc_reader port map ( clk_i => clk_i, reset_i => reset_s, irc_i => irc_i(3), reset_index_event_i => reset_index_event_s(3), reset_index_event2_i => reset_index_event2_s(3), reset_ab_error_i => reset_ab_error_s(3), irc_o => irc_o_s(3) ); irc4 : irc_reader port map ( clk_i => clk_i, reset_i => reset_s, irc_i => irc_i(4), reset_index_event_i => reset_index_event_s(4), reset_index_event2_i => reset_index_event2_s(4), reset_ab_error_i => reset_ab_error_s(4), irc_o => irc_o_s(4) ); irc5 : irc_reader port map ( clk_i => clk_i, reset_i => reset_s, irc_i => irc_i(5), reset_index_event_i => reset_index_event_s(5), reset_index_event2_i => reset_index_event2_s(5), reset_ab_error_i => reset_ab_error_s(5), irc_o => irc_o_s(5) ); irc6 : irc_reader port map ( clk_i => clk_i, reset_i => reset_s, irc_i => irc_i(6), reset_index_event_i => reset_index_event_s(6), reset_index_event2_i => reset_index_event2_s(6), reset_ab_error_i => reset_ab_error_s(6), irc_o => irc_o_s(6) ); irc7 : irc_reader port map ( clk_i => clk_i, reset_i => reset_s, irc_i => irc_i(7), reset_index_event_i => reset_index_event_s(7), reset_index_event2_i => reset_index_event2_s(7), reset_ab_error_i => reset_ab_error_s(7), irc_o => irc_o_s(7) ); irc_proc : irc_proc_main generic map ( num_irc_g => 8 ) port map ( clk_i => clk_i, reset_i => reset_s, -- IRC irc_i(0) => irc_o_s(0).count, irc_i(1) => irc_o_s(1).count, irc_i(2) => irc_o_s(2).count, irc_i(3) => irc_o_s(3).count, irc_i(4) => irc_o_s(4).count, irc_i(5) => irc_o_s(5).count, irc_i(6) => irc_o_s(6).count, irc_i(7) => irc_o_s(7).count, irc_index_reset_o => reset_index_event_s, -- BRAM mem_clk_i => clk_i, mem_en_i => irc_en_s, mem_we_i => irc_bls_s, mem_addr_i => irc_addr_s, mem_data_i => data_i, mem_data_o => irc_data_s ); reset_s <= reset_reg_r or reset_i; wire_in: process(next_ce_i, ce_s, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s) begin -- init values irc_en_s <= '0'; irc_out_s <= '0'; irc_bls_s <= (others => '0'); irc_addr_s <= (others => '0'); reset_ab_error_s <= (others => '0'); reset_index_event2_s <= (others => '0'); state_o_s <= (others => '0'); reset_reg_s <= '0'; reset_reg_wr_s <= '0'; -- Incoming bus request if next_ce_i = '1' then -- Mapping: -- 0 & axis & irc / index - (all read from bram) (R/W) -- 1 & axis & 0 - status register (R/W) -- 1 & 000 & 1 - reset if address_i(4) = '0' then irc_addr_s <= address_i(3 downto 0); irc_en_s <= '1'; irc_bls_s <= bls_i; irc_out_s <= '1'; -- Maybe these would be better to latch in next_ce_i cycle, -- and then just pass them elsif address_i(0) = '0' then state_o_s(0) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.mark; state_o_s(1) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.ab_error; state_o_s(2) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.index_event; state_o_s(3) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.index; if bls_i(0) = '1' then if data_i(1) = '1' then reset_ab_error_s(to_integer(unsigned(address_i(3 downto 1)))) <= '1'; end if; if data_i(2) = '1' then reset_index_event2_s(to_integer(unsigned(address_i(3 downto 1)))) <= '1'; end if; end if; elsif address_i = "10001" then if bls_i(0) = '1' then reset_reg_s <= data_i(0); reset_reg_wr_s <= '1'; else -- Ugh, hack :-) state_o_s(0) <= reset_reg_r; state_o_s(3 downto 1) <= (others => '0'); end if; end if; end if; end process; wire_out: process(ce_s, irc_data_s, irc_out_r, state_o_r) begin data_o <= (others => '0'); if ce_s = '1' then if irc_out_r = '1' then data_o <= irc_data_s; else data_o(3 downto 0) <= state_o_r; end if; end if; end process; update: process begin wait until clk_i'event and clk_i= '1'; ce_s <= next_ce_i; irc_out_r <= irc_out_s; state_o_r <= state_o_s; if reset_i = '1' then reset_reg_r <= '1'; elsif reset_reg_wr_s = '1' then reset_reg_r <= reset_reg_s; end if; end process; end Behavioral;