hw/bus_irc.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_unsigned.all;
   4 use ieee.numeric_std.all;
   5 use work.mbl_Pkg.all;
   6 use work.lx_rocon_pkg.all;
   7
   8 -- IRC bus interconnect
   9 entity bus_irc is
  10         port
  11         (
  12                 clk_i        : in std_logic;
  13                 reset_i      : in std_logic;
  14                 -- Address (needs just last 4 bits, rest is wired to CE)
  15                 address_i    : in std_logic_vector(3 downto 0);
  16                 ce_i         : in std_logic;
  17                 -- Data bus
  18                 data_i       : in std_logic_vector(31 downto 0);
  19                 data_o       : out std_logic_vector(31 downto 0);
  20                 -- Bus signals
  21                 rd_i         : in std_logic;
  22                 bls_i        : in std_logic_vector(3 downto 0);
  23                 ta_o         : out std_logic;
  24                 -- Signals for IRC
  25                 irc1_i       : in IRC_INPUT_Type;
  26                 irc2_i       : in IRC_INPUT_Type;
  27                 irc3_i       : in IRC_INPUT_Type;
  28                 irc4_i       : in IRC_INPUT_Type;
  29                 -- Secondary data bus (slave)
  30                 address_2_i  : in std_logic_vector(3 downto 0);
  31                 ce_2_i       : in std_logic;
  32                 --
  33                 rd_2_i       : in std_logic;
  34                 bls_2_i      : in std_logic_vector(3 downto 0);
  35                 ta_2_o       : out std_logic
  36         );
  37 end bus_irc;
  38
  39 architecture Behavioral of bus_irc is
  40
  41         signal irc1_s, irc2_s, irc3_s, irc4_s : IRC_OUTPUT_Type;
  42         signal reset_index_event_s            : std_logic_vector(3 downto 0);
  43         signal reset_ab_error_s               : std_logic_vector(3 downto 0);
  44         signal irc_en_s                       : std_logic;
  45         signal irc_bls_s                      : std_logic_vector(3 downto 0);
  46         signal irc_addr_s                     : std_logic_vector(2 downto 0);
  47         signal irc_data_s                     : std_logic_vector(31 downto 0);
  48
  49 begin
  50
  51         irc1 : irc_reader
  52         port map
  53         (
  54                 clk_i               => clk_i,
  55                 reset_i             => reset_i,
  56                 irc_i               => irc1_i,
  57                 reset_index_event_i => reset_index_event_s(0),
  58                 reset_ab_error_i    => reset_ab_error_s(0),
  59                 irc_o               => irc1_s
  60         );
  61
  62         irc2 : irc_reader
  63         port map
  64         (
  65                 clk_i               => clk_i,
  66                 reset_i             => reset_i,
  67                 irc_i               => irc2_i,
  68                 reset_index_event_i => reset_index_event_s(1),
  69                 reset_ab_error_i    => reset_ab_error_s(1),
  70                 irc_o               => irc2_s
  71         );
  72
  73         irc3 : irc_reader
  74         port map
  75         (
  76                 clk_i               => clk_i,
  77                 reset_i             => reset_i,
  78                 irc_i               => irc3_i,
  79                 reset_index_event_i => reset_index_event_s(2),
  80                 reset_ab_error_i    => reset_ab_error_s(2),
  81                 irc_o               => irc3_s
  82         );
  83
  84         irc4 : irc_reader
  85         port map
  86         (
  87                 clk_i               => clk_i,
  88                 reset_i             => reset_i,
  89                 irc_i               => irc4_i,
  90                 reset_index_event_i => reset_index_event_s(3),
  91                 reset_ab_error_i    => reset_ab_error_s(3),
  92                 irc_o               => irc4_s
  93         );
  94
  95         irc_proc : irc_proc_main
  96         port map
  97         (
  98                 clk_i              => clk_i,
  99                 reset_i            => reset_i,
 100                 irc1_i.qcount      => irc1_s.qcount,
 101                 irc1_i.index       => irc1_s.index,
 102                 irc1_i.index_event => irc1_s.index_event,
 103                 irc2_i.qcount      => irc2_s.qcount,
 104                 irc2_i.index       => irc2_s.index,
 105                 irc2_i.index_event => irc2_s.index_event,
 106                 irc3_i.qcount      => irc3_s.qcount,
 107                 irc3_i.index       => irc3_s.index,
 108                 irc3_i.index_event => irc3_s.index_event,
 109                 irc4_i.qcount      => irc4_s.qcount,
 110                 irc4_i.index       => irc4_s.index,
 111                 irc4_i.index_event => irc4_s.index_event,
 112                 irc_index_reset_o  => reset_index_event_s,
 113                 -- BRAM access (the other port)
 114                 mem_clk_i          => clk_i,
 115     mem_en_i           => irc_en_s,
 116     mem_we_i           => irc_bls_s,
 117     mem_addr_i         => irc_addr_s,
 118     mem_data_i         => data_i,
 119     mem_data_o         => irc_data_s
 120         );
 121
 122 wire:
 123         process(ce_i, ce_2_i, rd_i, rd_2_i, bls_i, bls_2_i, address_i, address_2_i, irc_data_s, irc1_s, irc2_s, irc3_s, irc4_s, data_i)
 124                 variable ce_v      : std_logic;
 125                 variable rd_v      : std_logic;
 126                 variable bls_v     : std_logic_vector(3 downto 0);
 127                 variable address_v : std_logic_vector(3 downto 0);
 128         begin
 129
 130                 -- init values
 131                 data_o           <= (others => 'X');
 132                 irc_en_s         <= '0';
 133                 irc_bls_s        <= (others => '0');
 134                 irc_addr_s       <= (others => 'X');
 135                 reset_ab_error_s <= (others => '0');
 136
 137                 -- init variables
 138                 ce_v        := ce_i or ce_2_i;
 139
 140                 if ce_i = '1' then
 141                         rd_v      := rd_i;
 142                         bls_v     := bls_i;
 143                         address_v := address_i;
 144                 elsif ce_2_i = '1' then
 145                         rd_v      := rd_2_i;
 146                         bls_v     := bls_2_i;
 147                         address_v := address_2_i;
 148                 else
 149                         rd_v      := '0';
 150                         bls_v     := (others => '0');
 151                         address_v := (others => '0');
 152                 end if;
 153
 154                 -- Bus request
 155                 if ce_v = '1' then
 156                         -- Mapping:
 157                         -- 0 & axis & irc / index - (all read from bram) (R/w)
 158                         -- 1 & axis & 0           - status register (R/W)
 159                         if address_v(3) = '0' then
 160                                 irc_addr_s  <= address_i(2 downto 0);
 161                                 irc_en_s    <= '1';
 162                                 irc_bls_s   <= bls_i;
 163                                 data_o      <= irc_data_s;
 164                         elsif address_v(0) = '0' then
 165                                 if rd_v = '1' then
 166
 167                                         case address_v(2 downto 1) is
 168                                                 when "00" =>
 169                                                         data_o(0)       <= irc1_s.mark;
 170                                                         data_o(1)       <= irc1_s.ab_error;
 171                                                 when "01" =>
 172                                                         data_o(0)       <= irc2_s.mark;
 173                                                         data_o(1)       <= irc2_s.ab_error;
 174                                                 when "10" =>
 175                                                         data_o(0)       <= irc3_s.mark;
 176                                                         data_o(1)       <= irc3_s.ab_error;
 177                                                 when "11" =>
 178                                                         data_o(0)       <= irc4_s.mark;
 179                                                         data_o(1)       <= irc4_s.ab_error;
 180                                                 when others =>
 181                                                         null;
 182                                         end case;
 183
 184                                         data_o(31 downto 2) <= (others => '0');
 185
 186                                 elsif bls_v(0) = '1' and data_i(0) = '1' then
 187                                         reset_ab_error_s(to_integer(unsigned(address_v(2 downto 1)))) <= '1';
 188                                 end if;
 189                         end if;
 190
 191                 end if;
 192         end process;
 193
 194 ta:
 195         process(clk_i)
 196         begin
 197                 if clk_i = '1' and clk_i'event then
 198                         ta_o <= rd_i;
 199
 200                         if rd_i = '0' and rd_2_i = '1' then
 201                                 ta_2_o <= rd_2_i;
 202                         else
 203                                 ta_2_o <= '0';
 204                         end if;
 205
 206                 end if;
 207         end process;
 208
 209 end Behavioral;
 210