3 #include <system_def.h>
10 #include "appl_version.h"
11 #include "appl_fpga.h"
13 #define SWAB32(x) ((x >> 24) | ((x & 0x00FF0000) >> 8) | ((x & 0x0000FF00) << 8) | (x << 24))
15 /* Registers in FPGA */
16 volatile uint32_t *tumbl_control = (volatile uint32_t *)FPGA_TUMBL_CONTROL_REG;
17 volatile uint32_t *tumbl_trace_kick = (volatile uint32_t *)FPGA_TUMBL_TRACE_KICK_REG;
18 volatile uint32_t *tumbl_pc = (volatile uint32_t *)FPGA_TUMBL_PC;
19 volatile uint32_t *tumbl_base = (volatile uint32_t *)FPGA_TUMBL_IMEM_BASE;
20 volatile uint32_t *tumbl_imem = (volatile uint32_t *)FPGA_TUMBL_IMEM_BASE;
21 volatile uint32_t *tumbl_dmem = (volatile uint32_t *)FPGA_TUMBL_DMEM_BASE;
23 volatile struct irc_register *irc1 = (volatile struct irc_register *)FPGA_IRC1_BASE;
24 volatile struct irc_register *irc2 = (volatile struct irc_register *)FPGA_IRC2_BASE;
25 volatile struct irc_register *irc3 = (volatile struct irc_register *)FPGA_IRC3_BASE;
26 volatile struct irc_register *irc4 = (volatile struct irc_register *)FPGA_IRC4_BASE;
28 /* Variables for configuration */
29 volatile uint16_t *fpga_configure_line = (volatile uint16_t *)0x8003FFFC;
30 int fpga_configured = 0;
31 int fpga_reconfiguration_locked = 1;
33 /* BUS calibration - registers to measure the delay necessary for reading and writing */
34 volatile uint32_t *fpga_bus_calib_read1 = (volatile uint32_t *)0x8003FFF0;
35 volatile uint32_t *fpga_bus_calib_read2 = (volatile uint32_t *)0x8003FFF4;
37 volatile uint32_t *fpga_bus_calib_write1 = (volatile uint32_t *)0x8003FFF8;
38 volatile uint32_t *fpga_bus_calib_write2 = (volatile uint32_t *)0x8003FFFC;
40 /* BUS calibration - values (shifting all bits) */
41 #define CALIB_VAL1 0xAAAAAAAA
42 #define CALIB_VAL2 0x55555555
46 /* Initialze EMC for FPGA */
50 * CS polarity: LOW (ATTENTION: Must match FPGA setup)
51 * Byte line state: Reads are only 32 bits
54 * Write protection: disabled
56 LPC_EMC->StaticConfig0 = 0x00000002;
58 /* Delays - not calibrated at this point
59 * We're running on 72 MHz, FPGA bus is running on 100 MHz async.
62 * Turnaround: 2 cycles (cca. 28 ns)
64 LPC_EMC->StaticWaitRd0 = 0x1F;
65 LPC_EMC->StaticWaitWr0 = 0x1F;
66 LPC_EMC->StaticWaitTurn0 = 0x01;
68 /* Shift addresses by 2 (32-bit bus) */
69 LPC_SC->SCS &= 0xFFFFFFFE;
71 printf("EMC for FPGA initialized!\n");
74 int appl_fpga_tumbl_set_reset(int reset)
79 *tumbl_control |= FPGA_TUMBL_CONTROL_REG_RESET_BIT;
81 *tumbl_control &= ~FPGA_TUMBL_CONTROL_REG_RESET_BIT;
85 int appl_fpga_tumbl_set_halt(int halt)
88 *tumbl_control |= FPGA_TUMBL_CONTROL_REG_HALT_BIT;
90 *tumbl_control &= ~FPGA_TUMBL_CONTROL_REG_HALT_BIT;
95 int appl_fpga_tumbl_set_trace(int trace)
98 *tumbl_control |= FPGA_TUMBL_CONTROL_REG_TRACE_BIT;
100 *tumbl_control &= ~FPGA_TUMBL_CONTROL_REG_TRACE_BIT;
105 int appl_fpga_tumbl_kick_trace()
109 *tumbl_trace_kick = 1;
112 /* Make sure it's processed */
113 for (i = 0; i < 32; i++)
117 printf("Tumbl PC: 0x%08X\n", (unsigned int) *tumbl_pc);
121 void appl_fpga_tumbl_write(unsigned int offset, unsigned char *ptr, int len)
124 unsigned int *iptr = (unsigned int *)ptr;
126 for (i = 0; i < len / 4; i++)
127 tumbl_base[(offset / 4) + i] = SWAB32(iptr[i]);
131 * Bus calibration - functions can be called via USB interface
136 * bus is not pipelined, therefore
137 * just necessary delay for I/O to enter
138 * high impedance state (synchronous clocking => only 1 cycle necessary)
141 /* Cannot be on stack due to memory barrier for gcc */
142 static uint32_t a, b;
144 int appl_fpga_calibrate_bus_read()
148 /* Set the delays are set to highest (default) value */
149 LPC_EMC->StaticWaitRd0 = 0x1F;
151 while (LPC_EMC->StaticWaitRd0 >= 0)
153 for (i = 0; i < 1024; i++)
155 /* Reset the values */
160 /* Read the values several times - so there are two flips at least
161 * NOTE: SDRAM reads / writes may occur in between!
163 a = *fpga_bus_calib_read1;
164 b = *fpga_bus_calib_read2;
165 a = *fpga_bus_calib_read1;
166 b = *fpga_bus_calib_read2;
167 a = *fpga_bus_calib_read1;
168 b = *fpga_bus_calib_read2;
169 a = *fpga_bus_calib_read1;
170 b = *fpga_bus_calib_read2;
174 if (a != CALIB_VAL1 || b != CALIB_VAL2)
176 if (LPC_EMC->StaticWaitRd0 == 0x1F)
178 printf("ERROR: FPGA bus is not working properly!\n");
183 LPC_EMC->StaticWaitRd0++;
184 printf("FPGA bus: StaticWaitRd0 set to 0x%02X\n", (unsigned int) LPC_EMC->StaticWaitRd0);
190 /* We're good, lower it */
191 if (LPC_EMC->StaticWaitRd0 == 0)
193 printf("FPGA bus: StaticWaitRd0 set to 0x%02X\n", (unsigned int) LPC_EMC->StaticWaitRd0);
197 LPC_EMC->StaticWaitRd0--;
203 int appl_fpga_calibrate_bus_write()
207 /* Set the delays are set to highest (default) value */
208 LPC_EMC->StaticWaitWr0 = 0x1F;
210 while (LPC_EMC->StaticWaitWr0 >= 0)
212 for (i = 0; i < 1024; i++)
214 /* Make sure there is nothing other going on */
216 *fpga_bus_calib_write1 = 0x00000000;
217 *fpga_bus_calib_write2 = 0x00000000;
222 /* Write the values several times - so there are two flips at least
223 * NOTE: SDRAM reads / writes may occur in between!
225 *fpga_bus_calib_write1 = CALIB_VAL1;
226 *fpga_bus_calib_write2 = CALIB_VAL2;
227 *fpga_bus_calib_write1 = CALIB_VAL1;
228 *fpga_bus_calib_write2 = CALIB_VAL2;
229 *fpga_bus_calib_write1 = CALIB_VAL1;
230 *fpga_bus_calib_write2 = CALIB_VAL2;
231 *fpga_bus_calib_write1 = CALIB_VAL1;
232 *fpga_bus_calib_write2 = CALIB_VAL2;
234 * Strongly ordered memory
235 * GCC is blocked by volatilness
238 a = *fpga_bus_calib_write1;
239 b = *fpga_bus_calib_write2;
243 if (a != CALIB_VAL1 || b != CALIB_VAL2)
245 if (LPC_EMC->StaticWaitWr0 == 0x1F)
247 printf("ERROR: FPGA bus is not working properly!\n");
248 printf("a = 0x%08X, b = 0x%08X\n", (unsigned int) a, (unsigned int) b);
253 LPC_EMC->StaticWaitWr0++;
254 printf("FPGA bus: StaticWaitWr0 set to 0x%02X\n", (unsigned int) LPC_EMC->StaticWaitWr0);
260 /* We're good, lower it */
261 if (LPC_EMC->StaticWaitWr0 == 0)
263 printf("FPGA bus: StaticWaitWr0 set to 0x%02X\n", (unsigned int) LPC_EMC->StaticWaitWr0);
267 LPC_EMC->StaticWaitWr0--;
273 void appl_fpga_set_reconfiguration_lock(int lock)
275 fpga_reconfiguration_locked = lock;
278 int appl_fpga_get_reconfiguration_lock()
280 return fpga_reconfiguration_locked;
283 int appl_fpga_configure()
290 if (fpga_configured && fpga_reconfiguration_locked)
291 return FPGA_CONF_ERR_RECONF_LOCKED;
293 /* Make sure INIT_B is set as input */
294 hal_gpio_direction_input(XC_INIT_PIN);
296 /* PROGRAM_B to low */
297 hal_gpio_set_value(XC_PROGRAM_PIN, 0);
299 /* SUSPEND to low (permamently) */
300 hal_gpio_set_value(XC_SUSPEND_PIN, 0);
302 /* Wait some cycles (minimum: 500 ns) */
303 for (i = 0; i < 4096; i++)
306 /* PROGRAM_B to high */
307 hal_gpio_set_value(XC_PROGRAM_PIN, 1);
309 /* Wait for INIT_B to be high */
312 while (!hal_gpio_get_value(XC_INIT_PIN))
316 hal_gpio_set_value(XC_SUSPEND_PIN, 1);
317 return FPGA_CONF_ERR_RESET_FAIL;
323 /* Use highest EMC delays */
324 LPC_EMC->StaticWaitRd0 = 0x1F;
325 LPC_EMC->StaticWaitWr0 = 0x1F;
327 /* Assert RWDR to WRITE */
328 hal_gpio_set_value(XC_RDWR_PIN, 0);
330 /* Send bin file (NOTE: Bits must be reversed!) via EMC)
335 * 3) send configuration data
338 * INIT_B is LOW in case of a failure
339 * DONE is HIGH in case of a success
341 * When DONE is HIGH, deassert RWDR and do GPIO reconfiguration:
343 * GPIOs need to be reconfigured:
345 * INIT_B - used as reset, triggered LOW right after startup,
346 * change from input to output (OUTPUT DRAIN)
350 magic = (char *)FPGA_CONFIGURATION_FILE_ADDRESS;
352 if (magic[0] != 'F' || magic[1] != 'P' || magic[2] != 'G' || magic[3] != 'A')
354 hal_gpio_set_value(XC_SUSPEND_PIN, 1);
358 size = (*(uint32_t *)(FPGA_CONFIGURATION_FILE_ADDRESS + 4)) >> 1;
359 data = (uint16_t *)(FPGA_CONFIGURATION_FILE_ADDRESS + 4 + sizeof(uint32_t));
361 /* Periodically check for failure */
367 *fpga_configure_line = *data;
372 if (!hal_gpio_get_value(XC_INIT_PIN))
374 hal_gpio_set_value(XC_SUSPEND_PIN, 1);
375 return FPGA_CONF_ERR_WRITE_ERR;
386 /* We're done, deassert RDWR */
387 hal_gpio_set_value(XC_RDWR_PIN, 1);
389 while (!hal_gpio_get_value(XC_DONE_PIN))
391 if (!hal_gpio_get_value(XC_INIT_PIN))
393 hal_gpio_set_value(XC_SUSPEND_PIN, 1);
394 return FPGA_CONF_ERR_CRC_ERR;
398 /* Issue startup clocks with data all 1s (at least 8 recommended) */
399 for (i = 0; i < 16; i++)
400 *fpga_configure_line = 0xFFFF;
402 /* In our design, INIT_B is used as reset, convert it to output, and trigger it */
403 hal_gpio_direction_output(XC_INIT_PIN, 0);
405 /* Hold it for some time */
406 for (i = 0; i < 128; i++)
409 /* Use EMC delays obtained through calibration */
410 LPC_EMC->StaticWaitRd0 = 0x04;
411 LPC_EMC->StaticWaitWr0 = 0x01;
414 hal_gpio_direction_output(XC_INIT_PIN, 1);
416 /* Give it some time */
417 for (i = 0; i < 1024; i++)
421 printf("FPGA configured!\n");
422 return FPGA_CONF_SUCESS;