hw/calibration_write_register.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5 use ieee.numeric_std.all;
   6
   7 -- Calibration write register
   8 -- Used to calibrate writing timing
   9
  10 entity calibration_write_register is
  11         port
  12         (
  13                 -- Clock
  14                 clk         : in std_logic;
  15
  16                 -- Reset
  17                 reset       : in std_logic;
  18
  19                 -- Chip enable
  20                 ce          : in std_logic;
  21
  22                 -- Data bus
  23                 data_in     : in std_logic_vector(31 downto 0);
  24                 data_out    : out std_logic_vector(31 downto 0);
  25
  26                 -- Bus signals
  27                 rd          : in std_logic;
  28                 bls         : in std_logic_vector(3 downto 0);
  29                 ta          : out std_logic
  30         );
  31 end calibration_write_register;
  32
  33 architecture Behavioral of calibration_write_register is
  34         signal value : std_logic_vector(31 downto 0);
  35 begin
  36
  37         -- Read is immideate
  38         memory_bus_read: process(ce, rd, value)
  39         begin
  40
  41                 -- Init defaults
  42                 ta <= '1';
  43                 data_out <= (others => 'X');
  44
  45                 if ce = '0' and rd = '0' then
  46                         ta <= '0';
  47                         data_out <= value;
  48                 end if;
  49
  50         end process;
  51
  52         -- Write waits for clock
  53         memory_bus_write: process(clk, reset)
  54         begin
  55
  56                 if reset = '1' then
  57                         value <= (others => '0');
  58                 end if;
  59
  60                 if clk = '1' and clk'event then
  61
  62                         if ce = '0' then
  63
  64                                 if reset = '0' and bls /= "1111" then
  65
  66                                         if bls(0) = '0' then
  67                                                 value(7 downto 0) <= data_in(7 downto 0);
  68                                         end if;
  69
  70                                         if bls(1) = '0' then
  71                                                 value(15 downto 8) <= data_in(15 downto 8);
  72                                         end if;
  73
  74                                         if bls(2) = '0' then
  75                                                 value(23 downto 16) <= data_in(23 downto 16);
  76                                         end if;
  77
  78                                         if bls(3) = '0' then
  79                                                 value(31 downto 24) <= data_in(31 downto 24);
  80                                         end if;
  81
  82                                 end if;
  83
  84                         end if;
  85
  86                 end if;
  87
  88         end process;
  89
  90 end Behavioral;
  91