From 5c8cb50ce62ea18abc2ef0998abf6aeeae12c92b Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sun, 15 Feb 2015 11:55:02 +0100 Subject: [PATCH] Simplify FPGA design external CPU read logic. Signed-off-by: Pavel Pisa --- hw/bus_example.vhd | 2 +- hw/lx_dad_top.vhd | 30 +++++++++++++----------------- 2 files changed, 14 insertions(+), 18 deletions(-) diff --git a/hw/bus_example.vhd b/hw/bus_example.vhd index c11eaeb..64ffa72 100644 --- a/hw/bus_example.vhd +++ b/hw/bus_example.vhd @@ -54,7 +54,7 @@ example_mem_instance: lx_example_mem dout_m => example_mem_dout_s ); -decoder_logic: process(ce_i, address_i) +decoder_logic: process(ce_i, address_i, bls_i) begin example_mem_ce_s <= '0'; example_mem_bls_s <= (others => '0'); diff --git a/hw/lx_dad_top.vhd b/hw/lx_dad_top.vhd index 2ee35f7..cde28dc 100644 --- a/hw/lx_dad_top.vhd +++ b/hw/lx_dad_top.vhd @@ -76,11 +76,8 @@ architecture Behavioral of lx_dad_top is signal cs0_xc_f_s : std_logic; signal rd_f_s : std_logic; -- Filtered RD signal i_rd_s : std_logic; -- Internal bus RD (active 1) - -- signal next_i_rd_s : std_logic; - signal last_i_rd_s : std_logic; -- Delayed RD bus, used for latching signal next_last_i_rd_s : std_logic; - signal i_rd_cycle2_s : std_logic; -- Some internal subsystems provide - signal next_i_rd_cycle2_s : std_logic; -- data only after 2 cycles + signal last_i_rd_s : std_logic; -- Delayed RD bus, used for latching -- signal address_f_s : std_logic_vector(15 downto 0); -- Filtered address -- @@ -163,12 +160,11 @@ dff_reset: dff2 -- Bus update memory_bus_logic: - process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_cycle2_s, last_i_rd_s, + process(cs0_xc_f_s, rd_f_s, last_rd_s, last_i_rd_s, bls_f_s, last_bls_s, data_f_s, data_write_s, data_o_s, data_read_s, last_address_s, address_f_s) begin -- Defaults - next_i_rd_cycle2_s <= '0'; next_address_hold_s <= '0'; -- Check if we have chip select @@ -179,13 +175,9 @@ memory_bus_logic: -- Internal read if last_rd_s = '0' or (last_address_s /= address_f_s) then i_rd_s <= '1'; - next_i_rd_cycle2_s <= '1'; - next_last_i_rd_s <= '1'; - elsif i_rd_cycle2_s = '1' then -- FIXME it seems that some internal - i_rd_s <= '1'; -- peripherals demands 2 cycles to read next_last_i_rd_s <= '1'; else - i_rd_s <= '0'; + i_rd_s <= '0'; next_last_i_rd_s <= '0'; end if; @@ -271,8 +263,6 @@ memory_bus_update: last_bls_s <= next_last_bls_s; last_rd_s <= next_last_rd_s; i_bls_s <= next_i_bls_s; - -- i_rd_s <= next_i_rd_s; - i_rd_cycle2_s <= next_i_rd_cycle2_s; last_i_rd_s <= next_last_i_rd_s; data_write_s <= next_data_write_s; last_address_s <= next_last_address_s; @@ -282,7 +272,7 @@ memory_bus_update: -- Do the actual wiring here memory_bus_wiring: - process(cs0_xc_f_s, i_bls_s, address_f_s, example_out_s, meas_out_s) + process(cs0_xc_f_s, i_bls_s, address_f_s, example_out_s, meas_out_s, i_rd_s, last_i_rd_s) begin -- Inactive by default @@ -290,7 +280,7 @@ memory_bus_wiring: meas_ce_s <= '0'; data_o_s <= (others => '0'); - if cs0_xc_f_s = '1' or i_bls_s /= "0000" then + if i_rd_s = '1' or i_bls_s /= "0000" then -- Memory Map (16-bit address @ 32-bit each) @@ -301,14 +291,20 @@ memory_bus_wiring: if address_f_s < "0001000000000000" then -- Tumbl example_ce_s <= '1'; - data_o_s <= example_out_s; elsif address_f_s(15 downto 2) = "00011111111111" then -- Measurement meas_ce_s <= '1'; - data_o_s <= meas_out_s; end if; end if; + if last_i_rd_s = '1' then + if address_f_s < "0001000000000000" then -- Tumbl + data_o_s <= example_out_s; + elsif address_f_s(15 downto 2) = "00011111111111" then -- Measurement + data_o_s <= meas_out_s; + end if; + end if; + end process; -- If RD and BLS is not high, we must keep DATA at high impedance -- 2.39.2