From 4de2acbdb1328172d19ae102d98b44820902015f Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Tue, 3 Nov 2015 12:18:13 +0100 Subject: [PATCH] Update DAD hardware testbed. Signed-off-by: Pavel Pisa --- hw/tb/Makefile | 5 +- hw/tb/lx_dad_top_tb.vhd | 107 ++++++++++++++++++++++++++-------------- hw/tb/test-lx-dad.gtkw | 27 ++++++---- 3 files changed, 90 insertions(+), 49 deletions(-) diff --git a/hw/tb/Makefile b/hw/tb/Makefile index 537c798..f96b113 100644 --- a/hw/tb/Makefile +++ b/hw/tb/Makefile @@ -5,7 +5,8 @@ lx_util_SRC=util_pkg.vhd lx_dad_pkg.vhd xilinx_dualport_bram.vhd lx_util_DIR=.. lx_dad_SRC=dff3.vhd dff2.vhd cnt_div.vhd measurement_register.vhd \ lx_crosdom_ser_fifo.vhd \ - bus_example.vhd lx_example_mem.vhd bus_measurement.vhd lx_dad_top.vhd + bus_example.vhd lx_example_mem.vhd bus_measurement.vhd lx_dad_top.vhd \ + clockgen.vhd bus_sensor.vhd sensor_mem.vhd lx_adc_if.vhd lx_dad_DIR=.. MODULES=lx_util lx_dad @@ -32,7 +33,7 @@ all: test-lx-dad test-lx-dad: analyze-all #imem.bits $(GHDL) $(GHDLFLAGS) -m $(ANALYZEFLAGS) lx_dad_top_tb - $(GHDL) $(GHDLFLAGS) -r lx_dad_top_tb --stop-time=10000ns --vcd=$@.vcd --wave=$@.ghw + $(GHDL) $(GHDLFLAGS) -r lx_dad_top_tb --stop-time=1000000ns --vcd=$@.vcd --wave=$@.ghw analyze-all: $(SRC) $(GHDL) $(GHDLFLAGS) -a $(ANALYZEFLAGS) $(SRC) diff --git a/hw/tb/lx_dad_top_tb.vhd b/hw/tb/lx_dad_top_tb.vhd index 401bf7f..a033b1f 100644 --- a/hw/tb/lx_dad_top_tb.vhd +++ b/hw/tb/lx_dad_top_tb.vhd @@ -15,15 +15,28 @@ ARCHITECTURE behavior OF lx_dad_top_tb IS COMPONENT lx_dad_top PORT( --clk_cpu : IN std_logic; - clk_50m : IN std_logic; + clk_50m : IN std_logic; cs0_xc : IN std_logic; rd : IN std_logic; bls : IN std_logic_vector(3 downto 0); address : IN std_logic_vector(15 downto 0); data : INOUT std_logic_vector(31 downto 0); - init : IN std_logic - ); + init : IN std_logic; + + -- signal connected to external JK FF + event_jk_j : out std_logic; + -- signals to image sensor + phi1 : out std_logic; + phi2 : out std_logic; + phi_rst : out std_logic; + LED_1 : out std_logic; + sck_o : out std_logic; + cnv_o : out std_logic; + phist : out std_logic; + sck_i : in std_logic; + SDI : in std_logic + ); END COMPONENT; @@ -44,19 +57,33 @@ ARCHITECTURE behavior OF lx_dad_top_tb IS --constant clk_period_cpu : time := 13.8 ns; constant clk_period_50m : time := 20 ns; + signal adc_sck : std_logic; + BEGIN - -- Instantiate the Unit Under Test (UUT) + -- Instantiate the Unit Under Test (UUT) uut: lx_dad_top PORT MAP ( --clk_cpu => clk_cpu, - clk_50m => clk_50m, + clk_50m => clk_50m, cs0_xc => cs0_xc, rd => rd, bls => bls, address => address, data => data, - init => init + init => init, + + event_jk_j => open, + -- signals to image sensor + phi1 => open, + phi2 => open, + phi_rst => open, + LED_1 => open, + sck_o => open, + cnv_o => open, + phist => open, + sck_i => adc_sck, + SDI => adc_sck ); -- Clock process definitions @@ -91,6 +118,28 @@ BEGIN -- variable bits_line : LINE; -- variable mem_location : bit_vector(31 downto 0); -- variable imem_fill_addr : natural range 0 to 2**8-1 := 0; + + procedure mcu_write( + constant addr: std_logic_vector(15 downto 0); + constant wrdata: std_logic_vector(31 downto 0) + ) is + begin + wait until clk_50m'event and clk_50m = '1'; + wait until clk_50m'event and clk_50m = '0'; + rd <= '1'; + address <= addr; + data <= wrdata; + bls <= "0000"; + cs0_xc <= '0'; + wait until clk_50m'event and clk_50m = '1'; + wait until clk_50m'event and clk_50m = '1'; + wait until clk_50m'event and clk_50m = '1'; + cs0_xc <= '1'; + bls <= "1111"; + data <= (others => 'Z'); + wait until clk_50m'event and clk_50m = '1'; + end mcu_write; + begin -- Assert LX_DAD system reset for 3 clock cycles @@ -123,22 +172,20 @@ BEGIN --end loop fill_loop; -- Write to example bus memory - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '0'; - address <= x"0004"; - data <= x"12345678"; - bls <= "0000"; - cs0_xc <= '0'; - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '1'; - cs0_xc <= '1'; - rd <= '1'; - data <= x"abcdef01"; - bls <= "1111"; - data <= (others => 'Z'); - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '1'; + mcu_write(x"1000", x"00000000"); + + mcu_write(x"1001", x"00000009"); -- 9 + mcu_write(x"1002", x"00000020"); -- 399 + mcu_write(x"1003", x"00000020"); -- 409 + mcu_write(x"1004", x"00000020"); -- 399 + mcu_write(x"1005", x"00000009"); -- 9 + mcu_write(x"1006", x"00000040"); -- 599 + mcu_write(x"1007", x"00000050"); -- 609 + mcu_write(x"1008", x"00000050"); -- 5023999 + mcu_write(x"1009", x"00000008"); -- 499 + + mcu_write(x"1000", x"00000009"); + -- mcu_write(x"1000", x"00000011"); -- Simulate external master accesses example bus memory xmem_loop: loop @@ -154,22 +201,6 @@ BEGIN cs0_xc <= '1'; rd <= '1'; bls <= "1111"; - - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '0'; - address <= x"0004"; - rd <= '0'; - cs0_xc <= '0'; - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '1'; - wait until clk_50m'event and clk_50m = '0'; - cs0_xc <= '1'; - rd <= '1'; - bls <= "1111"; end loop xmem_loop; wait; diff --git a/hw/tb/test-lx-dad.gtkw b/hw/tb/test-lx-dad.gtkw index 97fe9d7..710d42e 100644 --- a/hw/tb/test-lx-dad.gtkw +++ b/hw/tb/test-lx-dad.gtkw @@ -1,20 +1,21 @@ [*] [*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI -[*] Sun Feb 15 02:38:56 2015 +[*] Tue Nov 3 11:17:10 2015 [*] -[dumpfile] "/mnt/sshfs/pc-pisa/home/pi/repo/lx-dad/hw/tb/test-lx-dad.ghw" -[dumpfile_mtime] "Sun Feb 15 02:35:59 2015" -[dumpfile_size] 38278 -[savefile] "/mnt/sshfs/pc-pisa/home/pi/repo/lx-dad/hw/tb/test-lx-dad.gtkw" -[timestart] 606700000 -[size] 1000 600 +[dumpfile] "/home/pi/repo/ulan/lx-dad/hw/tb/test-lx-dad.ghw" +[dumpfile_mtime] "Tue Nov 3 10:45:48 2015" +[dumpfile_size] 4081875 +[savefile] "/home/pi/repo/ulan/lx-dad/hw/tb/test-lx-dad.gtkw" +[timestart] 0 +[size] 1153 694 [pos] -1 -1 -*-27.000000 860000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-37.000000 342740000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] top. +[treeopen] top.lx_dad_top_tb. [sst_width] 210 [signals_width] 166 [sst_expanded] 1 -[sst_vpaned_height] 154 +[sst_vpaned_height] 186 @28 top.lx_dad_top_tb.uut.clk_50m @22 @@ -33,5 +34,13 @@ top.lx_dad_top_tb.uut.memory_bus_example.example_mem_ce_r #{top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[31:0]} top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[31] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[30] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[29] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[28] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[27] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[26] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[25] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[24] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[23] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[22] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[21] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[20] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[19] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[18] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[17] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[16] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[15] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[14] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[13] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[12] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[11] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[10] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[9] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[8] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[7] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[6] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[5] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[4] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[3] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[2] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[1] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[0] #{top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[31:0]} top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[31] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[30] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[29] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[28] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[27] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[26] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[25] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[24] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[23] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[22] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[21] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[20] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[19] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[18] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[17] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[16] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[15] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[14] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[13] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[12] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[11] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[10] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[9] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[8] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[7] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[6] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[5] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[4] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[3] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[2] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[1] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[0] #{top.lx_dad_top_tb.uut.data_read_s[31:0]} top.lx_dad_top_tb.uut.data_read_s[31] top.lx_dad_top_tb.uut.data_read_s[30] top.lx_dad_top_tb.uut.data_read_s[29] top.lx_dad_top_tb.uut.data_read_s[28] top.lx_dad_top_tb.uut.data_read_s[27] top.lx_dad_top_tb.uut.data_read_s[26] top.lx_dad_top_tb.uut.data_read_s[25] top.lx_dad_top_tb.uut.data_read_s[24] top.lx_dad_top_tb.uut.data_read_s[23] top.lx_dad_top_tb.uut.data_read_s[22] top.lx_dad_top_tb.uut.data_read_s[21] top.lx_dad_top_tb.uut.data_read_s[20] top.lx_dad_top_tb.uut.data_read_s[19] top.lx_dad_top_tb.uut.data_read_s[18] top.lx_dad_top_tb.uut.data_read_s[17] top.lx_dad_top_tb.uut.data_read_s[16] top.lx_dad_top_tb.uut.data_read_s[15] top.lx_dad_top_tb.uut.data_read_s[14] top.lx_dad_top_tb.uut.data_read_s[13] top.lx_dad_top_tb.uut.data_read_s[12] top.lx_dad_top_tb.uut.data_read_s[11] top.lx_dad_top_tb.uut.data_read_s[10] top.lx_dad_top_tb.uut.data_read_s[9] top.lx_dad_top_tb.uut.data_read_s[8] top.lx_dad_top_tb.uut.data_read_s[7] top.lx_dad_top_tb.uut.data_read_s[6] top.lx_dad_top_tb.uut.data_read_s[5] top.lx_dad_top_tb.uut.data_read_s[4] top.lx_dad_top_tb.uut.data_read_s[3] top.lx_dad_top_tb.uut.data_read_s[2] top.lx_dad_top_tb.uut.data_read_s[1] top.lx_dad_top_tb.uut.data_read_s[0] +@29 +top.lx_dad_top_tb.uut.phist +@28 +top.lx_dad_top_tb.uut.phi_rst +top.lx_dad_top_tb.uut.phi1 +top.lx_dad_top_tb.uut.phi2 +top.lx_dad_top_tb.uut.sck_o +top.lx_dad_top_tb.uut.cnv_o [pattern_trace] 1 [pattern_trace] 0 -- 2.39.2