From 217e4a7a6c6bb4adeb62e207e3b38a37a901a8ce Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sun, 15 Feb 2015 03:49:22 +0100 Subject: [PATCH 1/1] Include example of mapping dualported RAM mapping to example component. Signed-off-by: Pavel Pisa --- hw/bus_example.vhd | 52 +++++++++++++++++++++++++++++++++- hw/lx_dad_pkg.vhd | 21 ++++++++++++++ hw/lx_dad_top.prj | 1 + hw/lx_example_mem.vhd | 65 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 138 insertions(+), 1 deletion(-) create mode 100644 hw/lx_example_mem.vhd diff --git a/hw/bus_example.vhd b/hw/bus_example.vhd index 333c487..ea14f5e 100644 --- a/hw/bus_example.vhd +++ b/hw/bus_example.vhd @@ -31,8 +31,58 @@ end bus_example; architecture Behavioral of bus_example is + signal example_mem_ce_s : std_logic; + signal example_mem_ce_r : std_logic; + signal example_mem_bls_s : std_logic_vector(3 downto 0); + signal example_mem_dout_s : std_logic_vector(31 downto 0); begin - data_o <= (others => '0'); +example_mem_instance: lx_example_mem + port map + ( + -- Memory wiring for internal state automata use + clk_i => clk_i, + ce_i => '0', + adr_i => (others => '0'), + bls_i => (others => '0'), + dat_i => (others => '0'), + dat_o => open, + -- Memory wiring for Master CPU + clk_m => clk_i, + en_m => example_mem_ce_s, + we_m => example_mem_bls_s, + addr_m => address_i(9 downto 0), + din_m => data_i, + dout_m => example_mem_dout_s + ); + +decoder_logic: process(ce_i, address_i) + begin + example_mem_ce_s <= '0'; + example_mem_bls_s <= (others => '0'); + + if ce_i = '1' and address_i(11 downto 10) = "00" then + example_mem_ce_s <= '1'; + example_mem_bls_s <= bls_i; + end if; + end process; + +output_multiplexer: process(example_mem_ce_r, example_mem_dout_s) + begin + data_o <= (others => '0'); + + if example_mem_ce_r = '1' then + data_o <= example_mem_dout_s; + end if; + end process; + +sync_update: + process + begin + wait until clk_i = '1' and clk_i'event; + + example_mem_ce_r <= example_mem_ce_s; + end process; + end Behavioral; diff --git a/hw/lx_dad_pkg.vhd b/hw/lx_dad_pkg.vhd index de69d2c..387c822 100644 --- a/hw/lx_dad_pkg.vhd +++ b/hw/lx_dad_pkg.vhd @@ -115,6 +115,27 @@ package lx_dad_pkg is ); end component; + -- Dualported memory for example componenet + component lx_example_mem + port + ( + -- Memory wiring for internal state automata use + clk_i : in std_logic; + ce_i : in std_logic; + adr_i : in std_logic_vector(9 downto 0); + bls_i : in std_logic_vector(3 downto 0); + dat_i : in std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + -- Memory wiring for Master CPU + clk_m : in std_logic; + en_m : in std_logic; + we_m : in std_logic_vector(3 downto 0); + addr_m : in std_logic_vector(9 downto 0); + din_m : in std_logic_vector(31 downto 0); + dout_m : out std_logic_vector(31 downto 0) + ); + end component; + -- Measurement interconnect component bus_measurement port diff --git a/hw/lx_dad_top.prj b/hw/lx_dad_top.prj index 5693fcb..f438017 100644 --- a/hw/lx_dad_top.prj +++ b/hw/lx_dad_top.prj @@ -8,4 +8,5 @@ vhdl work "measurement_register.vhd" vhdl work "lx_crosdom_ser_fifo.vhd" vhdl work "bus_measurement.vhd" vhdl work "bus_example.vhd" +vhdl work "lx_example_mem.vhd" vhdl work "lx_dad_top.vhd" diff --git a/hw/lx_example_mem.vhd b/hw/lx_example_mem.vhd new file mode 100644 index 0000000..89e8e85 --- /dev/null +++ b/hw/lx_example_mem.vhd @@ -0,0 +1,65 @@ +library ieee; + +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use work.lx_dad_pkg.all; + +-- 8 kB data memory for internal state automata +-- Can be accessed from the Master CPU + +entity lx_example_mem is + port + ( + -- Memory wiring for internal state automata use + clk_i : in std_logic; + ce_i : in std_logic; + adr_i : in std_logic_vector(9 downto 0); + bls_i : in std_logic_vector(3 downto 0); + dat_i : in std_logic_vector(31 downto 0); + dat_o : out std_logic_vector(31 downto 0); + -- Memory wiring for Master CPU + clk_m : in std_logic; + en_m : in std_logic; + we_m : in std_logic_vector(3 downto 0); + addr_m : in std_logic_vector(9 downto 0); + din_m : in std_logic_vector(31 downto 0); + dout_m : out std_logic_vector(31 downto 0) + ); +end lx_example_mem; + +architecture rtl of lx_example_mem is +begin + +I_RAMB: xilinx_dualport_bram + generic map + ( + we_width => 4, + byte_width => 8, + address_width => 10, + port_a_type => READ_FIRST, + port_b_type => READ_FIRST + ) + port map + ( + -- Internal state automata port + clka => clk_i, + rsta => '0', + ena => ce_i, + wea => bls_i, + addra => adr_i, + dina => dat_i, + douta => dat_o, + + -- Master CPU port + clkb => clk_m, + rstb => '0', + enb => en_m, + web => we_m, + addrb => addr_m, + dinb => din_m, + doutb => dout_m + ); + +end rtl; -- 2.39.2