From: Pavel Pisa Date: Tue, 27 Oct 2015 17:34:15 +0000 (+0100) Subject: Clean DAD test code a little to use symbolic names for registers and bits. X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/lx-cpu1/lx-dad.git/commitdiff_plain/273cac9ca1ed1567753498c2567f2bed3fd5a853 Clean DAD test code a little to use symbolic names for registers and bits. Signed-off-by: Pavel Pisa --- diff --git a/sw/app/lx_dad/appl_fpga.c b/sw/app/lx_dad/appl_fpga.c index 8c9647c..d99778a 100644 --- a/sw/app/lx_dad/appl_fpga.c +++ b/sw/app/lx_dad/appl_fpga.c @@ -12,6 +12,13 @@ #define SWAB32(x) ((x >> 24) | ((x & 0x00FF0000) >> 8) | ((x & 0x0000FF00) << 8) | (x << 24)) +/* Registers in FPGA */ + +volatile uint32_t *fpga_dad_ctrl_reg = FPGA_DAD_CTRL_REG; +volatile uint32_t *fpga_dad_sens_timing = FPGA_DAD_SENS_TIMING; +volatile uint32_t *fpga_dad_result_bank0 = FPGA_DAD_RESULT_BANK0; +volatile uint32_t *fpga_dad_result_bank1 = FPGA_DAD_RESULT_BANK1; + /* Variables for configuration */ volatile uint16_t *fpga_configure_line = (volatile uint16_t *)0x80007FF0; int fpga_configured = 0; diff --git a/sw/app/lx_dad/appl_fpga.h b/sw/app/lx_dad/appl_fpga.h index 1d92e1d..3c8dd8d 100644 --- a/sw/app/lx_dad/appl_fpga.h +++ b/sw/app/lx_dad/appl_fpga.h @@ -5,6 +5,26 @@ /* Register defines */ +#define FPGA_DAD_CTRL_REG 0x80004000 +#define FPGA_DAD_SENS_TIMING 0x80004004 +#define FPGA_DAD_RESULT_BANK0 0x80008000 +#define FPGA_DAD_RESULT_BANK1 0x80009000 + +extern volatile uint32_t *fpga_dad_ctrl_reg; +extern volatile uint32_t *fpga_dad_sens_timing; +extern volatile uint32_t *fpga_dad_result_bank0; +extern volatile uint32_t *fpga_dad_result_bank1; + +/* Control/status register bits */ + +#define FPGA_DAD_CTRL_CR_m 0x01 /* Continuous read */ +#define FPGA_DAD_CTRL_SR_m 0x02 /* Single read */ +#define FPGA_DAD_CTRL_BANK_m 0x04 /* Bank 1 / Bank 0 */ +#define FPGA_DAD_CTRL_STD_m 0x08 /* Standard operation */ +#define FPGA_DAD_CTRL_LEAK_m 0x10 /* Leak measurement mode */ +#define FPGA_DAD_CTRL_MULT_m 0x20 /* Multiple reads per single diode */ +#define FPGA_DAD_CTRL_FIN_m 0x40 /* Single read finished */ + /* Configuration defines */ #define FPGA_CONFIGURATION_FILE_ADDRESS 0xA1C00000 diff --git a/sw/app/lx_dad/appl_tests.c b/sw/app/lx_dad/appl_tests.c index 50ebfad..0e6e09f 100644 --- a/sw/app/lx_dad/appl_tests.c +++ b/sw/app/lx_dad/appl_tests.c @@ -1,8 +1,10 @@ #include #include +#include #include #include #include +#include #include #include #include @@ -17,6 +19,15 @@ #include #include "appl_defs.h" +#include "appl_fpga.h" + +FILE *cmd_io_as_direct_file(cmd_io_t *cmd_io, const char *mode) +{ + if (cmd_io->priv.ed_line.io_stack) + cmd_io = cmd_io->priv.ed_line.io_stack; + + return cmd_io_as_file(cmd_io, mode); +} int cmd_do_test_memusage(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) { @@ -35,14 +46,11 @@ int cmd_do_test_adc(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) { FILE *F; - if (cmd_io->priv.ed_line.io_stack) - cmd_io = cmd_io->priv.ed_line.io_stack; - - F = cmd_io_as_file(cmd_io, "r+"); + F = cmd_io_as_direct_file(cmd_io, "r+"); if (F == NULL) return CMDERR_EIO; - fprintf(F, "ADC: %ld %ld %ld %ld %ld\n", (LPC_ADC->DR[0] & 0xFFF0) >> 4, + fprintf(F, "ADC: %ld %ld %ld %ld %ld\r\n", (LPC_ADC->DR[0] & 0xFFF0) >> 4, (LPC_ADC->DR[1] & 0xFFF0) >> 4, (LPC_ADC->DR[2] & 0xFFF0) >> 4, (LPC_ADC->DR[3] & 0xFFF0) >> 4, @@ -71,7 +79,7 @@ int cmd_do_test_loglevel_cb(ul_log_domain_t *domain, void *context) cmd_io_t *cmd_io = (cmd_io_t *)context; s[sizeof(s)-1]=0; - snprintf(s,sizeof(s)-1,"%s (%d)\n\r",domain->name, domain->level); + snprintf(s,sizeof(s)-1,"%s (%d)\r\n",domain->name, domain->level); cmd_io_puts(cmd_io, s); return 0; } @@ -276,145 +284,201 @@ int cmd_do_goaddr(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) return 0; } -int cmd_do_mujtest(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) +typedef struct dad_status_bit_des_t { + unsigned int mask; + const char *label; +} dad_status_bit_des_t; + +dad_status_bit_des_t dad_status_bit_des[] = { + {FPGA_DAD_CTRL_CR_m, "CR"}, + {FPGA_DAD_CTRL_SR_m, "SR"}, + {FPGA_DAD_CTRL_BANK_m,"BANK"}, + {FPGA_DAD_CTRL_STD_m, "STD"}, + {FPGA_DAD_CTRL_LEAK_m,"LEAK"}, + {FPGA_DAD_CTRL_MULT_m,"MULT"}, + {FPGA_DAD_CTRL_FIN_m, "FIN"}, + {0, NULL} +}; + +int cmd_do_dadstatus(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) { - volatile uint32_t *testaddr = (volatile uint32_t *)0x80004000; - int p; - p=*testaddr++; - printf("read %d\n", p); - p=*testaddr++; - printf("read %d\n", p); - p=*testaddr++; - printf("read %d\n", p); - p=*testaddr++; - printf("read %d\n", p); - p=*testaddr++; - printf("read %d\n", p); - p=*testaddr++; - printf("read %d\n", p); - p=*testaddr++; - printf("read %d\n", p); - p=*testaddr++; - printf("read %d\n", p); - p=*testaddr++; - printf("read %d\n", p); - + uint32_t ctrlstat = *fpga_dad_ctrl_reg; + volatile uint32_t *timreg = fpga_dad_sens_timing; + int val; + int i; + FILE *F; + dad_status_bit_des_t *bdes; + + F = cmd_io_as_direct_file(cmd_io, "r+"); + if (F == NULL) + return CMDERR_EIO; + + fprintf(F, "DAD_STATUS=0x%02"PRIx32"\r\n", ctrlstat); + + for (bdes = dad_status_bit_des; bdes->mask; bdes++) { + fprintf(F, " %*s", (int)strlen(bdes->label), + bdes->mask & ctrlstat? bdes->label: "-"); + } + fprintf(F, "\r\n"); + + for (i = 1; i <= 9; i++) { + val = timreg[i - 1]; + fprintf(F, "TIMREG%d=%d\r\n", i, val); + } + + fclose(F); + return 0; } -int cmd_do_zmer(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) +int cmd_do_single(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) { - volatile uint32_t *testaddr = (volatile uint32_t *)0x80004000; - int32_t values[2048]; - uint32_t status, status_old, bank,i; - int32_t val; - status_old = *testaddr; - //while((status_old & (1<<2))==(status & (1<<2))) status=*testaddr; - //while (*testaddr &(1<<6)); - *testaddr = 0x12; - while (!(*testaddr & (1<<6))) printf("\ncekam\n"); - status = *testaddr; - testaddr = (volatile uint32_t *)0x80008000; - if (status&(1<<2)){ - // printf("bank1\n"); - testaddr = (volatile uint32_t *)0x80009000; - } else { - //printf("bank0\n"); - } - for(i=0;i<1024;i++){ - // values[i]=*testaddr++; - val=*testaddr++; - val+=(1<<17); - val&=(1<<18)-1; - val -= (1<<17); - values[i]=val; - } - if (status&(1<<2)){ - printf("bank1\n"); - //testaddr = (volatile uint32_t *)0x80008000; - } else { - printf("bank0\n"); - } - for (i=0;i<1024;i++){ - if (i==1024){ - printf("bank1\n"); - } - printf("%d\n",values[i]); - - } - printf("konec\n"); - - return 0; + volatile uint32_t *testaddr; + int32_t values[2048]; + uint32_t status, status_old, i; + int32_t val; + FILE *F; + + F = cmd_io_as_direct_file(cmd_io, "r+"); + if (F == NULL) + return CMDERR_EIO; + + testaddr = fpga_dad_ctrl_reg; + status_old = *testaddr; + //while((status_old & (1<<2))==(status & (1<<2))) status=*testaddr; + //while (*testaddr &(1<<6)); + *testaddr = FPGA_DAD_CTRL_LEAK_m | FPGA_DAD_CTRL_SR_m; + while (!(*testaddr & FPGA_DAD_CTRL_FIN_m)) + fprintf(F, "\r\ncekam\r\n"); + + status = *testaddr; + if (status & FPGA_DAD_CTRL_BANK_m) { + testaddr = fpga_dad_result_bank1; + } else { + testaddr = fpga_dad_result_bank0; + } + for(i=0;i<1024;i++){ + // values[i]=*testaddr++; + val=*testaddr++; + val+=(1<<17); + val&=(1<<18)-1; + val -= (1<<17); + values[i]=val; + } + if (status & FPGA_DAD_CTRL_BANK_m) { + fprintf(F, "bank1\r\n"); + } else { + fprintf(F, "bank0\r\n"); + } + for (i=0;i<1024;i++){ + if (i==1024){ + fprintf(F, "bank1\r\n"); + } + fprintf(F, "%"PRId32"\r\n",values[i]); + } + fprintf(F, "end\r\n"); + + fclose(F); + + return 0; } -int cmd_do_runnung_meas(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]){ - volatile uint32_t *testaddr = (volatile uint32_t *)0x80004000; - int32_t values[1024]; - uint32_t status, status_old, bank,i; - int32_t val; - status_old = *testaddr; - status = *testaddr; - while((status_old & (1<<2))==(status & (1<<2))) {status=*testaddr; printf("dely %i %i",status_old & (1<<2),status & (1<<2));} - if (status&(1<<2)){ - testaddr = (volatile uint32_t *)0x80009000; - } else { - testaddr = (volatile uint32_t *)0x80008000; - } - for(i=0;i<1024;i++){ - // values[i]=*testaddr++; - val=*testaddr++; - val+=(1<<17); - val&=(1<<18)-1; - val -= (1<<17); - values[i]=-1*val; - } - if (status&(1<<2)){ - printf("bank1\n"); - //testaddr = (volatile uint32_t *)0x80008000; - } else { - printf("bank0\n"); - } - //printf("zacatek\n"); - for (i=0;i<1024;i++){ - printf("%d\n",values[i]); - } - printf("konec\n"); - return 0; +int cmd_do_running_meas(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]){ + volatile uint32_t *testaddr; + int32_t values[1024]; + uint32_t status, status_old, i; + int32_t val; + int32_t wcycles = 0; + FILE *F; + + F = cmd_io_as_direct_file(cmd_io, "r+"); + //F = stdout; + if (F == NULL) + return CMDERR_EIO; + + testaddr = fpga_dad_ctrl_reg; + status_old = *testaddr; + status = *testaddr; + while((status_old & FPGA_DAD_CTRL_BANK_m) == (status & FPGA_DAD_CTRL_BANK_m)) { + status = *testaddr; + wcycles++; + if (wcycles > 10000000) { + fprintf(F, "scan wait timeout\r\n"); + fprintf(F, "timeout status 0x%02"PRIx32" old 0x%02"PRIx32"\r\n", + status, status_old); + fclose(F); + return CMDERR_TIMEOUT; + } + } + if (status & (1 << 2)) { + testaddr = fpga_dad_result_bank1; + } else { + testaddr = fpga_dad_result_bank0; + } + for(i=0; i<1024; i++) { + // values[i]=*testaddr++; + val = *testaddr++; + val += (1 << 17); + val &= (1 << 18) - 1; + val -= (1 << 17); + values[i] = -1 * val; + } + fprintf(F, "bank%d status 0x%02"PRIx32" old 0x%02"PRIx32 + " wait cycles %"PRId32"\r\n", + status & FPGA_DAD_CTRL_BANK_m? 1: 0, + status, status_old, wcycles); + for (i=0;i<1024;i++){ + fprintf(F, "%"PRId32"\r\n",values[i]); + } + fprintf(F, "end\r\n"); + + fclose(F); + + return 0; } int cmd_do_init(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) { - printf("init!\n"); - volatile uint32_t *testaddr = (volatile uint32_t *)0x80004000; - *testaddr++ = 0x9; -// *testaddr++; - *testaddr++ = 9; - *testaddr++ = 399; - *testaddr++ = 409; - *testaddr++ = 399; - *testaddr++ = 9; - *testaddr++ = 599; - *testaddr++ = 609; - //*testaddr++ = 4879; - *testaddr++ = 5023999; - *testaddr=499; - - printf("OK!\n"); - return 0; + FILE *F; + + F = cmd_io_as_direct_file(cmd_io, "r+"); + + fprintf(F, "init!\r\n"); + volatile uint32_t *testaddr = fpga_dad_sens_timing; + + *fpga_dad_ctrl_reg = FPGA_DAD_CTRL_STD_m; + +// *testaddr++; + *testaddr++ = 9; + *testaddr++ = 399; + *testaddr++ = 409; + *testaddr++ = 399; + *testaddr++ = 9; + *testaddr++ = 599; + *testaddr++ = 609; + //*testaddr++ = 4879; + *testaddr++ = 5023999; + *testaddr=499; + + *fpga_dad_ctrl_reg = FPGA_DAD_CTRL_STD_m | FPGA_DAD_CTRL_CR_m; + + fprintf(F, "OK!\r\n"); + fclose(F); + return 0; } int cmd_do_send(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) { - char *end; - volatile uint32_t *testaddr = (volatile uint32_t *)0x80004000; - int read; - int p=(int) strtol(param[1], &end, 10); - testaddr+=p; - p=(int) strtol(end, &end, 10); - *testaddr=p; - read=*testaddr; - printf("sent %d & read %d\n", p, read); - return 0; + char *end; + volatile uint32_t *testaddr = fpga_dad_ctrl_reg; + int read; + int p=(int) strtol(param[1], &end, 10); + testaddr+=p; + p=(int) strtol(end, &end, 10); + *testaddr=p; + read=*testaddr; + printf("sent %d & read %d\n", p, read); + return 0; } cmd_des_t const cmd_des_test_memusage={0, 0, @@ -462,19 +526,30 @@ cmd_des_t const cmd_des_testmpu={0, 0, cmd_des_t const cmd_des_goaddr={0, 0, "goaddr","run from address", cmd_do_goaddr,{(void*)0}}; - -cmd_des_t const cmd_des_mujtest={0,0,"mujtest","run my simple test", cmd_do_mujtest,{(void*)0}}; -cmd_des_t const cmd_des_zmer={0,0,"zmer","read values from spectrometer (2 readouts)", cmd_do_zmer,{(void*)0x12}}; +cmd_des_t const cmd_des_dadstatus={0, 0, + "dadstatus", "show status of DAD subsystem", + cmd_do_dadstatus, {(void*)0}}; -cmd_des_t const cmd_des_scan={0,0,"scan","read values from spectrometer (2 readouts)", cmd_do_zmer,{(void*)0x10}}; +cmd_des_t const cmd_des_zmer={0, 0, + "zmer", "read values from spectrometer (2 readouts)", + cmd_do_single, {(void*)0x12}}; +cmd_des_t const cmd_des_scan={0, 0, + "scan", "read values from spectrometer (2 readouts)", + cmd_do_single, {(void*)0x10}}; -cmd_des_t const cmd_des_init={0,0,"init", "inicializacni vypis pro zacatek komunikace", cmd_do_init,{(void*)0}}; +cmd_des_t const cmd_des_init={0, 0, + "init", "inicializacni vypis pro zacatek komunikace", + cmd_do_init, {(void*)0}}; -cmd_des_t const cmd_des_sendvalue={0,0,"send", "send value to given address", cmd_do_send,{(void*)0}}; +cmd_des_t const cmd_des_sendvalue={0, 0, + "send", "send value to given address", + cmd_do_send, {(void*)0}}; -cmd_des_t const cmd_des_runnung_meas = {0,0,"run","read values from spectrometer (running)", cmd_do_runnung_meas,{(void*)0x10}}; +cmd_des_t const cmd_des_running_meas = {0, 0, + "run", "read values from spectrometer (running)", + cmd_do_running_meas, {(void*)0x10}}; cmd_des_t const *const cmd_appl_tests[]={ &cmd_des_test_memusage, @@ -489,12 +564,12 @@ cmd_des_t const *const cmd_appl_tests[]={ &cmd_des_testsdram, &cmd_des_testmpu, &cmd_des_goaddr, - &cmd_des_mujtest, + &cmd_des_dadstatus, &cmd_des_zmer, &cmd_des_scan, &cmd_des_init, &cmd_des_sendvalue, - & cmd_des_runnung_meas, + & cmd_des_running_meas, NULL };