library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.lx_dad_pkg.all;

-- Connects example memory

entity bus_example is
	port
	(
		-- Clock
		clk_i        : in std_logic;
		-- Chip enable
		ce_i         : in std_logic;
		-- Global Reset
		reset_i      : in std_logic;
		-- Master CPU peripheral bus
		bls_i        : in std_logic_vector(3 downto 0);
		address_i    : in std_logic_vector(11 downto 0);
		data_i       : in std_logic_vector(31 downto 0);
		data_o       : out std_logic_vector(31 downto 0)

		-- Non bus signals
		--
		-- Add there external component signals
  );
end bus_example;

architecture Behavioral of bus_example is

begin

	data_o <= (others => '0');

end Behavioral;