From e1481a8a5088575d2485c2125831ec09f2bb1f88 Mon Sep 17 00:00:00 2001 From: walt Date: Wed, 27 Mar 2013 06:33:37 +0000 Subject: [PATCH] Backport from mainline: 2013-03-27 Walter Lee * config/tilegx/tilegx.md (insn_mnz_): Replaced by ... (insn_mnz_v8qi): ... this ... (insn_mnz_v4hi): ... and this. Replace (const_int 0) with the vector equivalent. (insn_vmnz): Replaced by ... (insn_v1mnz): ... this ... (insn_v2mnz): ... and this. Replace (const_int 0) with the vector equivalent. (insn_mz_): Replaced by ... (insn_mz_v8qi): ... this ... (insn_mz_v4hi): ... and this. Replace (const_int 0) with the vector equivalent. (insn_vmz): Replaced by ... (insn_v1mz): ... this ... (insn_v2mz): ... and this. Replace (const_int 0) with the vector equivalent. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@197145 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 22 +++++ gcc/config/tilegx/tilegx.md | 156 ++++++++++++++++++++++++++++-------- 2 files changed, 145 insertions(+), 33 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 383df3efe07..f54855f2f9f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,25 @@ +2013-03-27 Walter Lee + + Backport from mainline: + 2013-03-27 Walter Lee + + * config/tilegx/tilegx.md (insn_mnz_): Replaced by ... + (insn_mnz_v8qi): ... this ... + (insn_mnz_v4hi): ... and this. Replace (const_int 0) with the + vector equivalent. + (insn_vmnz): Replaced by ... + (insn_v1mnz): ... this ... + (insn_v2mnz): ... and this. Replace (const_int 0) with the vector + equivalent. + (insn_mz_): Replaced by ... + (insn_mz_v8qi): ... this ... + (insn_mz_v4hi): ... and this. Replace (const_int 0) with the + vector equivalent. + (insn_vmz): Replaced by ... + (insn_v1mz): ... this ... + (insn_v2mz): ... and this. Replace (const_int 0) with the vector + equivalent. + 2013-03-26 Eric Botcazou * doc/invoke.texi (SPARC options): Remove -mlittle-endian. diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 73479e3c236..a5589c2a347 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -4343,57 +4343,147 @@ ;; insn_v1mz ;; insn_v2mnz ;; insn_v2mz -(define_insn "insn_mnz_" - [(set (match_operand:VEC48MODE 0 "register_operand" "=r") - (if_then_else:VEC48MODE - (ne:VEC48MODE - (match_operand:VEC48MODE 1 "reg_or_0_operand" "rO") - (const_int 0)) - (match_operand:VEC48MODE 2 "reg_or_0_operand" "rO") - (const_int 0)))] - "" - "vmnz\t%0, %r1, %r2" +(define_insn "insn_mnz_v8qi" + [(set (match_operand:V8QI 0 "register_operand" "=r") + (if_then_else:V8QI + (ne:V8QI + (match_operand:V8QI 1 "reg_or_0_operand" "rO") + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (match_operand:V8QI 2 "reg_or_0_operand" "rO") + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)])))] + "" + "v1mnz\t%0, %r1, %r2" [(set_attr "type" "X01")]) -(define_expand "insn_vmnz" +(define_expand "insn_v1mnz" [(set (match_operand:DI 0 "register_operand" "") - (if_then_else:VEC48MODE - (ne:VEC48MODE + (if_then_else:V8QI + (ne:V8QI (match_operand:DI 1 "reg_or_0_operand" "") - (const_int 0)) + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)]) + ) (match_operand:DI 2 "reg_or_0_operand" "") - (const_int 0)))] + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)])))] "" { - tilegx_expand_builtin_vector_binop (gen_insn_mnz_, mode, - operands[0], mode, operands[1], + tilegx_expand_builtin_vector_binop (gen_insn_mnz_v8qi, V8QImode, + operands[0], V8QImode, operands[1], + operands[2], true); + DONE; +}) + +(define_insn "insn_mz_v8qi" + [(set (match_operand:V8QI 0 "register_operand" "=r") + (if_then_else:V8QI + (ne:V8QI + (match_operand:V8QI 1 "reg_or_0_operand" "rO") + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)]) + (match_operand:V8QI 2 "reg_or_0_operand" "rO")))] + "" + "v1mz\t%0, %r1, %r2" + [(set_attr "type" "X01")]) + +(define_expand "insn_v1mz" + [(set (match_operand:DI 0 "register_operand" "") + (if_then_else:V8QI + (ne:V8QI + (match_operand:DI 1 "reg_or_0_operand" "") + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)]) + (match_operand:DI 2 "reg_or_0_operand" "")))] + "" +{ + tilegx_expand_builtin_vector_binop (gen_insn_mz_v8qi, V8QImode, + operands[0], V8QImode, operands[1], operands[2], true); DONE; }) -(define_insn "insn_mz_" - [(set (match_operand:VEC48MODE 0 "register_operand" "=r") - (if_then_else:VEC48MODE - (ne:VEC48MODE - (match_operand:VEC48MODE 1 "reg_or_0_operand" "rO") - (const_int 0)) - (const_int 0) - (match_operand:VEC48MODE 2 "reg_or_0_operand" "rO")))] +(define_insn "insn_mnz_v4hi" + [(set (match_operand:V4HI 0 "register_operand" "=r") + (if_then_else:V4HI + (ne:V4HI + (match_operand:V4HI 1 "reg_or_0_operand" "rO") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (match_operand:V4HI 2 "reg_or_0_operand" "rO") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])))] + "" + "v2mnz\t%0, %r1, %r2" + [(set_attr "type" "X01")]) + +(define_expand "insn_v2mnz" + [(set (match_operand:DI 0 "register_operand" "") + (if_then_else:V4HI + (ne:V4HI + (match_operand:DI 1 "reg_or_0_operand" "") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (match_operand:DI 2 "reg_or_0_operand" "") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])))] "" - "vmz\t%0, %r1, %r2" +{ + tilegx_expand_builtin_vector_binop (gen_insn_mnz_v4hi, V4HImode, + operands[0], V4HImode, operands[1], + operands[2], true); + DONE; +}) + +(define_insn "insn_mz_v4hi" + [(set (match_operand:V4HI 0 "register_operand" "=r") + (if_then_else:V4HI + (ne:V4HI + (match_operand:V4HI 1 "reg_or_0_operand" "rO") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)]) + (match_operand:V4HI 2 "reg_or_0_operand" "rO")))] + "" + "v2mz\t%0, %r1, %r2" [(set_attr "type" "X01")]) -(define_expand "insn_vmz" + +(define_expand "insn_v2mz" [(set (match_operand:DI 0 "register_operand" "") - (if_then_else:VEC48MODE - (ne:VEC48MODE + (if_then_else:V4HI + (ne:V4HI (match_operand:DI 1 "reg_or_0_operand" "") - (const_int 0)) - (const_int 0) + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)]) (match_operand:DI 2 "reg_or_0_operand" "")))] "" { - tilegx_expand_builtin_vector_binop (gen_insn_mz_, mode, - operands[0], mode, operands[1], + tilegx_expand_builtin_vector_binop (gen_insn_mz_v4hi, V4HImode, + operands[0], V4HImode, operands[1], operands[2], true); DONE; }) -- 2.39.2