From 73dd12c25f0ea5950d8105fff41f34c9a7b493dd Mon Sep 17 00:00:00 2001 From: abel Date: Mon, 1 Apr 2013 08:17:06 +0000 Subject: [PATCH] Backport from mainline 2013-02-27 Andrey Belevantsev PR middle-end/45472 * sel-sched-ir.c (merge_expr): Also change vinsn of merged expr when the may_trap_p bit of the exprs being merged differs. Reorder tests for speculativeness in the logical and operator. Backport from mainline 2013-03-05 Jakub Jelinek PR middle-end/56461 * sel-sched-ir.c (free_sched_pools): Release succs_info_pool.stack[succs_info_pool.max_top] vectors too if succs_info_pool.max_top isn't -1. Backport from mainline 2013-02-27 Andrey Belevantsev PR middle-end/45472 * gcc.dg/pr45472.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@197299 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 19 ++++++++++ gcc/sel-sched-ir.c | 10 ++++-- gcc/testsuite/ChangeLog | 8 +++++ gcc/testsuite/gcc.dg/pr45472.c | 63 ++++++++++++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr45472.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 33d54ab3ea5..c870a060ead 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2013-04-01 Andrey Belevantsev + + Backport from mainline + 2013-02-27 Andrey Belevantsev + + PR middle-end/45472 + + * sel-sched-ir.c (merge_expr): Also change vinsn of merged expr + when the may_trap_p bit of the exprs being merged differs. + Reorder tests for speculativeness in the logical and operator. + + Backport from mainline + 2013-03-05 Jakub Jelinek + + PR middle-end/56461 + * sel-sched-ir.c (free_sched_pools): Release + succs_info_pool.stack[succs_info_pool.max_top] vectors too + if succs_info_pool.max_top isn't -1. + 2013-04-01 Andrey Belevantsev Backport from mainline diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c index 74089df38d7..fe667210ec3 100644 --- a/gcc/sel-sched-ir.c +++ b/gcc/sel-sched-ir.c @@ -1862,8 +1862,12 @@ merge_expr (expr_t to, expr_t from, insn_t split_point) /* Make sure that speculative pattern is propagated into exprs that have non-speculative one. This will provide us with consistent speculative bits and speculative patterns inside expr. */ - if (EXPR_SPEC_DONE_DS (to) == 0 - && EXPR_SPEC_DONE_DS (from) != 0) + if ((EXPR_SPEC_DONE_DS (from) != 0 + && EXPR_SPEC_DONE_DS (to) == 0) + /* Do likewise for volatile insns, so that we always retain + the may_trap_p bit on the resulting expression. */ + || (VINSN_MAY_TRAP_P (EXPR_VINSN (from)) + && !VINSN_MAY_TRAP_P (EXPR_VINSN (to)))) change_vinsn_in_expr (to, EXPR_VINSN (from)); merge_expr_data (to, from, split_point); @@ -5019,7 +5023,7 @@ free_sched_pools (void) free_alloc_pool (sched_lists_pool); gcc_assert (succs_info_pool.top == -1); - for (i = 0; i < succs_info_pool.max_top; i++) + for (i = 0; i <= succs_info_pool.max_top; i++) { VEC_free (rtx, heap, succs_info_pool.stack[i].succs_ok); VEC_free (rtx, heap, succs_info_pool.stack[i].succs_other); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 099241559a5..d608dd7fcd4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2013-04-01 Andrey Belevantsev + + Backport from mainline + 2013-02-27 Andrey Belevantsev + + PR middle-end/45472 + * gcc.dg/pr45472.c: New test. + 2013-03-26 Richard Biener Backport from mainline diff --git a/gcc/testsuite/gcc.dg/pr45472.c b/gcc/testsuite/gcc.dg/pr45472.c new file mode 100644 index 00000000000..d6cb6bce65a --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr45472.c @@ -0,0 +1,63 @@ +/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */ +/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */ + +struct S +{ + volatile long vl; + int i; +}; +struct S s1, s2; + +void +foo (int j, int c) +{ + int i; + for (i = 0; i <= j; i++) + { + if (c) + s2.vl += s1.vl; + s1 = s2; + } +} +/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */ +/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */ + +struct S +{ + volatile long vl; + int i; +}; +struct S s1, s2; + +void +foo (int j, int c) +{ + int i; + for (i = 0; i <= j; i++) + { + if (c) + s2.vl += s1.vl; + s1 = s2; + } +} +/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */ +/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */ + +struct S +{ + volatile long vl; + int i; +}; +struct S s1, s2; + +void +foo (int j, int c) +{ + int i; + for (i = 0; i <= j; i++) + { + if (c) + s2.vl += s1.vl; + s1 = s2; + } +} -- 2.39.2