]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/gcc-tumbl.git/blobdiff - libgcc/config/mbtumbl/mulsi3.S
Cleanup pipeline a bit, change cond. branching to BRC/BRCI
[fpga/lx-cpu1/gcc-tumbl.git] / libgcc / config / mbtumbl / mulsi3.S
index c573fe2e7577d5288a88a77819b87878c5762bbc..06d620dd97ccc62333e9757df214d297834cee80 100644 (file)
 __mulsi3:
        .frame  r1,0,r15
        add     r3,r0,r0
-       BEQI    r5,$L_Result_Is_Zero      # Multiply by Zero
-       BEQI    r6,$L_Result_Is_Zero      # Multiply by Zero
-       BGEId   r5,$L_R5_Pos 
+       BRCI    EQ,r5,$L_Result_Is_Zero      # Multiply by Zero
+       BRCI    EQ,r6,$L_Result_Is_Zero      # Multiply by Zero
+       BRCId   GE,r5,$L_R5_Pos 
        XOR     r4,r5,r6                  # Get the sign of the result
        RSUBI   r5,r5,0                   # Make r5 positive
 $L_R5_Pos:
-       BGEI    r6,$L_R6_Pos
+       BRCI    GE,r6,$L_R6_Pos
        RSUBI   r6,r6,0                   # Make r6 positive
 $L_R6_Pos:     
        bri     $L1
@@ -53,10 +53,10 @@ $L2:
 $L1:   
        srl     r6,r6
        addc    r7,r0,r0
-       beqi    r7,$L2
-       bneid   r6,$L2
+       brci    eq,r7,$L2
+       brcid   ne,r6,$L2
        add     r3,r3,r5        
-       blti    r4,$L_NegateResult                      
+       brci    lt,r4,$L_NegateResult                   
        rts     r15,4
 $L_NegateResult:
        rtsd    r15,4