Cleanup pipeline a bit, change cond. branching to BRC/BRCI

[fpga/lx-cpu1/gcc-tumbl.git] / libgcc / config / mbtumbl / moddi3.S

diff --git a/libgcc/config/mbtumbl/moddi3.S b/libgcc/config/mbtumbl/moddi3.S
index 2082a047a1c80f2284e51b285dcc220a351a617f..5088474f3574b416e4d47afaf3cb235182df64c6 100644 (file)
--- a/libgcc/config/mbtumbl/moddi3.S
+++ b/libgcc/config/mbtumbl/moddi3.S
@@ -46,15 +46,15 @@ __moddi3:
 
 #Check for Zero Value in the divisor/dividend
        OR      r9,r5,r6                        # Check for the op1 being zero
-       BEQID   r9,$LaResult_Is_Zero            # Result is zero
+       BRCID   EQ,r9,$LaResult_Is_Zero         # Result is zero
        OR      r9,r7,r8                        # Check for the dividend being zero
-       BEQI    r9,$LaDiv_By_Zero               # Div_by_Zero   # Division Error
-       BGEId   r5,$La1_Pos 
+       BRCI    EQ,r9,$LaDiv_By_Zero            # Div_by_Zero   # Division Error
+       BRCId   GE,r5,$La1_Pos 
        XOR     r27,r5,r7                       # Get the sign of the result
        RSUBI   r6,r6,0                         # Make dividend positive
        RSUBIC  r5,r5,0                         # Make dividend positive
 $La1_Pos:
-       BGEI    r7,$La2_Pos
+       BRCI    GE,r7,$La2_Pos
        RSUBI   r8,r8,0                         # Make Divisor Positive
        RSUBIC  r9,r9,0                         # Make Divisor Positive
 $La2_Pos:
@@ -67,7 +67,7 @@ $La2_Pos:
 $LaDIV1:
        ADD     r6,r6,r6
        ADDC    r5,r5,r5                        # left shift logical r5
-       BGEID   r5,$LaDIV1                      
+       BRCID   GE,r5,$LaDIV1                   
        ADDIK   r28,r28,-1
 $LaDIV2:
        ADD     r6,r6,r6
@@ -75,24 +75,24 @@ $LaDIV2:
        ADDC    r4,r4,r4        # Move that bit into the Mod register
        ADDC    r3,r3,r3        # Move carry into high mod register
        rsub    r18,r7,r3       # Compare the High Parts of Mod and Divisor
-       bnei    r18,$L_High_EQ
+       brci    ne,r18,$L_High_EQ
        rsub    r18,r6,r4       # Compare Low Parts only if Mod[h] == Divisor[h]
 $L_High_EQ:    
        rSUB    r26,r8,r4       # Subtract divisor[L] from Mod[L]
        rsubc   r25,r7,r3       # Subtract divisor[H] from Mod[H]
-       BLTi    r25,$LaMOD_TOO_SMALL
+       BRCi    LT,r25,$LaMOD_TOO_SMALL
        OR      r3,r0,r25       # move r25 to mod [h]
        OR      r4,r0,r26       # move r26 to mod [l]
        ADDI    r30,r30,1
        ADDC    r29,r29,r0
 $LaMOD_TOO_SMALL:
        ADDIK   r28,r28,-1
-       BEQi    r28,$LaLOOP_END
+       BRCi    EQ,r28,$LaLOOP_END
        ADD     r30,r30,r30             # Shift in the '1' into div [low]
        ADDC    r29,r29,r29             # Move the carry generated into high
        BRI     $LaDIV2   # Div2
 $LaLOOP_END:
-       BGEI    r27,$LaRETURN_HERE
+       BRCI    GE,r27,$LaRETURN_HERE
        rsubi   r30,r30,0
        rsubc   r29,r29,r0
        BRI     $LaRETURN_HERE