MBTumbl: Implement support for conditional execution

[fpga/lx-cpu1/binutils-tumbl.git] / opcodes / microblaze-opcm.h

diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 7d4f463307b869fbac21b4c6c9aff8169a79f2c3..04688595e3d8a2c3d0a50c613c6e5b0a2d002e33 100644 (file)
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -31,10 +31,11 @@ enum microblaze_instr
   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, muli,
   bsll, bsra, bsrl, bslli, bsrai, bsrli, or, and, xor,
   andn, sra, src, srl, sext8, sext16, mts, mfs, br, brd, brl,
-  bra, bral, beq, bne, bned, blt, ble, bgt, bge, ori, andi, xori, andni,
+  bra, bral, beq, bne, blt, ble, bgt, bge, ori, andi, xori, andni,
   imm, rts, rti, bri, brli, brai, brali, beqi, bnei, blti, blei, bgti,
   bgei, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
-  sbi, shi, swi, halt, invalid_inst
+  sbi, shi, swi, halt, it, itt, ite,
+  invalid_inst
 };
 
 #else
@@ -82,9 +83,10 @@ enum microblaze_instr_type
   return_inst, immediate_inst, special_inst, memory_load_inst,
   memory_store_inst, barrel_shift_inst,
 #ifndef ARCH_mbtumbl
-       anyware_inst,
+  anyware_inst,
 #else
-       halt_inst
+  halt_inst,
+  pseudo_inst
 #endif
 };
 
@@ -139,6 +141,29 @@ enum microblaze_instr_type
 #define REG_TLBHI 36868 /* MMU: TLB High reg.  */
 #define REG_TLBSX 36869 /* MMU: TLB Search Index reg.  */
 
+#else
+
+/* Tumbl conditions for it, itt, ite */
+
+#define COND_ALL 0
+#define COND_EQ  1
+#define COND_NE  2
+#define COND_LT  3
+#define COND_LE  4
+#define COND_GT  5
+#define COND_GE  6
+
+#define COND_LOW  0
+#define COND_MASK 0x7
+
+#define COND_TYPE_MASK 0x18
+#define COND_TYPE_LOW  3
+
+#define COND_TYPE_ALL 0
+#define COND_TYPE_IT  1
+#define COND_TYPE_ITT 2
+#define COND_TYPE_ITE 3
+
 #endif
 
 /* Alternate names for gen purpose regs.  */