MBTumbl: Implement support for conditional execution

[fpga/lx-cpu1/binutils-tumbl.git] / opcodes / microblaze-opc.h

diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index b982351b633abb67ab72b7355d82f0baa5d5994e..3be14a7f9d2b522fecde9c2165b361b87c298847 100644 (file)
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -65,9 +65,12 @@
 
 #else
 
-/* Halt instruction type */
+/* Halt instruction is IMM5 */
 #define INST_TYPE_IMM5 20
 
+/* Conditional pseudoinstruction */
+#define INST_TYPE_COND 21
+
 #endif
 
 #define INST_TYPE_NONE 25
@@ -90,6 +93,7 @@
 #define OPCODE_MASK_H2  0xFC1F0000  /* High 6 and bits 20-16.  */
 #define OPCODE_MASK_H12 0xFFFF0000  /* High 16.  */
 #define OPCODE_MASK_H4  0xFC0007FF  /* High 6 and low 11 bits.  */
+#define OPCODE_MASK_H4S 0xFC0007E0  /* High 6 and bits 11 - 6.  */
 #define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last 
                                       nibble of last byte for spr.  */
 #define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last 
@@ -139,9 +143,12 @@ struct op_code_struct
   {"cmp",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst },
   {"cmpu",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst },
 #else
-  {"cmp",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, cmp, arithmetic_inst },
-  {"cmpu",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000020, OPCODE_MASK_H4, cmpu, arithmetic_inst },
+  {"cmp",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4S, cmp, arithmetic_inst },
+  {"cmpu",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000020, OPCODE_MASK_H4S, cmpu, arithmetic_inst },
   {"cmpi",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x68000000, OPCODE_MASK_H, cmpi, arithmetic_inst },
+  {"it",    INST_TYPE_COND, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000008, OPCODE_MASK_H123A, it, pseudo_inst },
+  {"itt",   INST_TYPE_COND, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000010, OPCODE_MASK_H123A, itt, pseudo_inst },
+  {"ite",   INST_TYPE_COND, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000018, OPCODE_MASK_H123A, ite, pseudo_inst },
 #endif
   {"addkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst },
   {"rsubkc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst },