Reintroduce back delay slot for branching instruction

[fpga/lx-cpu1/binutils-tumbl.git] / opcodes / microblaze-opcm.h

diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index b1ec3ae34ffa1ebe4a799afb3dca818125b944bd..c81a21c479686e60c6153c7d1b226003a1684bc7 100644 (file)
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -29,13 +29,13 @@ enum microblaze_instr
 {
   add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu, cmpi, cmpui,
   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, muli,
-  bsll, bsra, bsrl, bslli, bsrai, bsrli, or, and, xor,
-  andn, sra, src, srl, sext8, sext16, mts, mfs, br, brd, brl,
-  bra, bral, beq, bne, blt, ble, bgt, bge, ori, andi, xori, andni,
-  imm, rts, rti, bri, brli, brai, brali, beqi, bnei, blti, blei, bgti,
-  bgei, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
-  sbi, shi, swi, halt, it, itt, ite, itu, ittu, iteu, iti, itti, itei,
-  itui, ittui, iteui,
+  bsll, bsra, bsrl, bslli, bsrai, bsrli, or, and, xor, andn, sra, src, srl,
+  sext8, sext16, mts, mfs, br, brl, bra, bral, beq, bne, blt, ble, bgt, bge,
+  brd, brld, brad, brald, beqd, bned, bltd, bled, bgtd, bged, ori, andi, xori, andni,
+  imm, rts, rti, bri, brli, brai, brali, beqi, bnei, blti, blei, bgti, bgei, rtsd, rtid,
+  brid, brlid, braid, bralid, beqid, bneid, bltid, bleid, bgtid, bgeid, lbu, lhu, lw,
+  lwx, sb, sh, sw, swx, lbui, lhui, lwi, sbi, shi, swi, halt, it, itt, ite, itu, ittu,
+  iteu, iti, itti, itei, itui, ittui, iteui,
   invalid_inst
 };