Merge tag 'pm-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[can-eth-gw-linux.git] / arch / arm / mach-omap2 / clkt_dpll.c

diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 8463cc3562450155ee1a5b6eee6f506ba9366d89..924c230f89484473f057246fb7f3a8b53a28c2bd 100644 (file)
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -16,7 +16,7 @@
 
 #include <linux/kernel.h>
 #include <linux/errno.h>
-#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 
 #include <asm/div64.h>
@@ -76,7 +76,7 @@
  * (assuming that it is counting N upwards), or -2 if the enclosing loop
  * should skip to the next iteration (again assuming N is increasing).
  */
-static int _dpll_test_fint(struct clk *clk, u8 n)
+static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
 {
        struct dpll_data *dd;
        long fint, fint_min, fint_max;
@@ -85,7 +85,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
        dd = clk->dpll_data;
 
        /* DPLL divider must result in a valid jitter correction val */
-       fint = __clk_get_rate(__clk_get_parent(clk)) / n;
+       fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
 
        if (cpu_is_omap24xx()) {
                /* Should not be called for OMAP2, so warn if it is called */
@@ -186,15 +186,15 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
 }
 
 /* Public functions */
-
-void omap2_init_dpll_parent(struct clk *clk)
+u8 omap2_init_dpll_parent(struct clk_hw *hw)
 {
+       struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        u32 v;
        struct dpll_data *dd;
 
        dd = clk->dpll_data;
        if (!dd)
-               return;
+               return -EINVAL;
 
        v = __raw_readl(dd->control_reg);
        v &= dd->enable_mask;
@@ -204,18 +204,18 @@ void omap2_init_dpll_parent(struct clk *clk)
        if (cpu_is_omap24xx()) {
                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                       clk_reparent(clk, dd->clk_bypass);
+                       return 1;
        } else if (cpu_is_omap34xx()) {
                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                       clk_reparent(clk, dd->clk_bypass);
+                       return 1;
        } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                       clk_reparent(clk, dd->clk_bypass);
+                       return 1;
        }
-       return;
+       return 0;
 }
 
 /**
@@ -232,7 +232,7 @@ void omap2_init_dpll_parent(struct clk *clk)
  * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
  * if the clock @clk is not a DPLL.
  */
-u32 omap2_get_dpll_rate(struct clk *clk)
+unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
 {
        long long dpll_clk;
        u32 dpll_mult, dpll_div, v;
@@ -288,8 +288,10 @@ u32 omap2_get_dpll_rate(struct clk *clk)
  * (expensive) function again.  Returns ~0 if the target rate cannot
  * be rounded, or the rounded rate upon success.
  */
-long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+               unsigned long *parent_rate)
 {
+       struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        int m, n, r, scaled_max_m;
        unsigned long scaled_rt_rp;
        unsigned long new_rate = 0;
@@ -303,7 +305,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
        dd = clk->dpll_data;
 
        ref_rate = __clk_get_rate(dd->clk_ref);
-       clk_name = __clk_get_name(clk);
+       clk_name = __clk_get_name(hw->clk);
        pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
                 clk_name, target_rate);